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Upgrade activities at Clermont-Ferrand

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Presentation on theme: "Upgrade activities at Clermont-Ferrand"— Presentation transcript:

1 Upgrade activities at Clermont-Ferrand
François Vazeille ATLAS upgrade meeting 2010 November 8th - Very similar to the talk given on October 1st even though there were progresses in various activities. - 5 activities in progress, some of them in collaboration or with discussions with other labs. • Laser 2 • High Voltage system • Mechanics of Drawers • Active Dividers • ASIC for 3in1 card  In collaboration with LIP, Pisa and CERN  Discussions with Chicago and other labs. 1/13

2 Laser 2  Works in 3 steps See the previous talk for the history
The Laser 2 will be an evolution of the present system using the spare Laser, in fact a new system: optics, monitoring (16 diodes), mechanics, electronics, DAQ.  Works in 3 steps • : studies at Clermont, then in the building 175. • : design and construction. • During shut down 2012 : installation and first commissioning. 2/13

3 Last status at Clermont-Ferrand by October 1st
• The new Laser at Clermont-Ferrand In the laser room • New mechanics and optical components ready, in particular easy and professional positioning of optics, + copies of electronics and DAQ also ready. In the mechanics workshop 3/13

4 (with a moveable mirror)
Status at Clermont-Ferrand by November 8th in the Laser room Laser head Photodiode box PMTs Several patch panels (Fibers, cables) Additional laser for the alignment of optics (with a moveable mirror) Electronics and DAQ Debugging in progress in very clean conditions: then shipment at CERN as soon as everything will be understood. Shutter 4/13

5  Next studies in 175 • To reproduce the ATLAS working. • To understand better the monitoring and the light distribution. • To conclude on the best solutions in 2011  final design on the Laser 2.  Sharing of works on the Laser 2 ( ) • Mechanics, optics, electronics and DAQ: Clermont-Ferrand. • Light distribution: LIP, Pisa (?). • Installation and commissioning: CERN, Clermont, LIP, Pisa. 5/13

6 High Voltage system 6 options as described in a previous talk (Tilecal upgrade 2009 November 10th): inside/outside Drawers. More detailed Note will be submitted to Tilecal  All the options or a part of them could be put in the LoI  Final choice later. 6/13

7 Mechanics of Drawers First goal is to answer to the question: is-it possible to use mini-Drawers? WARNING: it is not a question of ″feeling″ but an R&D study able to conclude YES or NO. The study is at several levels: - The improvement of the sliding: a factor 2 is expected. - The mechanical links in order to prevent a ″Zig Zag″ position when pushing. Making of 4 mini-Drawers loaded by metal to recover the usual weight and tests of several solutions about mechanical links and sliding. • Purchase of a dynamometer to test the forces. • Drawings are made, making under study. 7/13

8 Sliding improved using polyethylene. Mechanical links using dedicated springs. Big holes loaded by metal to recover the weight. Tests of sliding at CERN in two Tilecal module positions: - Vertical: building 175, - Horizontal: test beam (Other positions moving the Table ?). with a comparison with standard Drawers.  Conclusion expected well before the LoI (and not before Xmas as foreseen). 8/13

9 Nothing new wit respect to the last presentation:
Active Dividers Nothing new wit respect to the last presentation: milestones kept. Remind of the principle: active components on the last stages  linearity recovery at higher Luminosities.  Design working and tested on a prototype (Michel Crouau) Gain shift of a signal above a dc current (Min. bias) Old Dividers: ~1% non linearity at ~ 3 µA ~2% ~ 7.5 µA New Divider: ~1% non linearity at ~75 µA only 1.6% at ~150 µA 20 Cards produced with working tests on the renewed Divider Test Bench (Roméo Bonnefoy), including the tests of active components (Transistors). 9/13

10  Systematic study of performances from 20 bases
• Foreseen first on the PMT Test Bench, by comparing the 20 new bases with 20 old bases associated to the same 20 PMTs but unfortunately the PMT Test Bench is not available  new batches of PMTs (see the talk of Dominique). • Tests likely made on a dedicated set-up making a one by one comparison  conclusions before the end of 2010.  Radiation sensitivity of active parts • Use of available tests of LHCb at Clermont-Ferrand. • Use of ATLAS tables of component sensitivity to radiation (Ph. Farthouat): no guarantee to find our transistors. • Radiation tests in 2011 to organize. 10/13

11 ASIC for 3in1 cards Well advanced project in IBM 130 µm technology,
including now the calibration and the integrator  more details in talk of J.Lecoq.  Key points • Working in current and not in voltage  fitting the PMT output working  low noise, low sensitivity to voltage power supply. • Working at 80 MHz  another noise reduction property. • Only 1 voltage supply requested for the ASIC, plus likely 1 or 2 voltages for the DACs. • Low power consumption. • Low radiation sensitivity  choice of IBM technology by CERN. • Possibility of external adjustment of peaking time. • Possibility of the optimal filtering inside the ASIC (many samples at 80 Mhz).  Environment • DACs outside the ASIC but on the 3in1 card. • LV regulators on the 3in1 card. 11/13 • Design should be compatible with Chicago studies on the commands, data flow, interface (GBT) on the Drawer (Chicago, Stockholm, Valencia…).

12 First foundry waited for end November … or later: a CERN purchase…
 second foundry purchased before the return of the first one.  Installation of the test bench is scheduled. Works on the Integrator - Because of the large time constant  some components will be outside the ASIC (Capacitors for example), but the ADC will stay inside. - More precise specifications were needed  Mails to many Tilecal people and many replies: thank you to everybody! Other information requested about the best peaking time from the Tilecal detector point of view: as above, mails to many Tilecal people and many replies: thanks… knowing now that the ASIC can work properly in a range 20 to 60 ns, with the best performances at the lower values. Last request is to recover the software of the optimal filtering to put it in the simulations. 12/13

13 Conclusion • A lot of information and results will be available for the LoI, with several options in some cases, about the 5 R&D’s: - Laser 2. - HV system. - Mechanics of Drawers. - Active Dividers. - ASIC as front end on the 3in1 card. • Some parts will be almost completed at the end of this year. 13/13


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