1. Brief Intro to Make
CST494/ Gannod

2. Harry Koehnemann, Computing Studies
The make utility
The make utility is a tool for managing computer projects
make uses a descriptor file called a makefile that contains
all the dependency information
rules for building/creating targets
Most often, the makefile tells make how to compile and link a program
Harry Koehnemann, Computing Studies

3. Harry Koehnemann, Computing Studies
Makefile rules
rules have the following form:
target ... : prerequisites ...
<tab> command
<tab> ...
A target is usually the name of a file that is generated by a program
A prerequisite is a file that is used as input to create the target
A command is an action that make carries out
Harry Koehnemann, Computing Studies

4. Harry Koehnemann, Computing Studies
Prerequisites
A normal prerequisite says 2 things:
order of execution of build commands: any commands necessary to build any of a target's prerequisites will be fully executed before any commands necessary to build the target.
dependency relationship: if any prerequisite is newer than the target, then the target is considered out-of-date and must be rebuilt.
Harry Koehnemann, Computing Studies

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Simple Example
prog1 : file1.o file2.o file3.o  CC -o prog1 file1.o file2.o file3.o  file1.o : file1.cc mydefs.h  CC -c file1.cc  file2.o : file2.cc mydefs.h  CC -c file2.cc  file3.o : file3.cc  CC -c file3.cc 
Harry Koehnemann, Computing Studies

6. Harry Koehnemann, Computing Studies
Phony Targets
Phony targets allow “scripts” to be included in a makefile.
.PHONY tells Make which targets are not files. This avoids conflict with files of the same name, and improves performance.
If a phony target is included as a prerequisite for another target, it will be run every time that other target is required. Phony targets are never up-to-date.
Harry Koehnemann, Computing Studies

7. Harry Koehnemann, Computing Studies
Example
# Naming our phony targets
.PHONY: clean install
# Removing the executable and the object files
clean:
rm sample main.o example.o
echo clean: make complete
# Installing the final product
install:
cp sample /usr/local
echo install: make complete
Harry Koehnemann, Computing Studies

8. Harry Koehnemann, Computing Studies
Makefile variables
The syntax for declaring and setting a makefile variable is varname = variable contents
To call the variable, use $(varname).
# Defining the object files
OBJ = main.o example.o
# Linking object files
sample: $(OBJ)
cc -o sample $(OBJ)
Harry Koehnemann, Computing Studies

9. Predefined make variables
CC Compiler, defaults to cc.
CFLAGS Passed to $(CC)
LD Loader, defaults to ld
LDFLAGS Passed to $(LD)
Full name of the current target.
$? Files for current dependency which are out-of-date
$< The source file of the current (single) dependency
Harry Koehnemann, Computing Studies

10. Harry Koehnemann, Computing Studies
Variable example
# Basic Makefile with variables CC = g++ CFLAGS = -Wall -O2 COMPILE = $(CC) $(CFLAGS) -c all: myprog myprog: main.o file.o $(CC) -o myprog main.o file.o main.o: main.cpp $(COMPILE) -o main.o main.cpp file.o: file.cpp $(COMPILE) -o file.o file.cpp
Harry Koehnemann, Computing Studies

11. Harry Koehnemann, Computing Studies
Predefined Rules
some common rules are built into make.
for example, make knows that in order to create a .o file, it must use $(CC) -c on the corresponding .c file
OBJECTS = data.o main.o io.o
project1: $(OBJECTS)
cc $(OBJECTS) -o project1
data.o: data.h
main.o: data.h io.h
io.o: io.h
Harry Koehnemann, Computing Studies

12. Harry Koehnemann, Computing Studies
Multiple targets
you can put more than one file in the target section of the dependency rules
CFLAGS = -Aa -D_HPUX_SOURCE
OBJECTS = data.o main.o io.o
project1: $(OBJECTS)
cc $(OBJECTS) -o project1
data.o main.o: data.h
io.o main.o: io.h
Harry Koehnemann, Computing Studies

13. Harry Koehnemann, Computing Studies
Pattern Rules
A pattern rule is a concise way of specifying a rule for many files at once.
You specify a pattern by using the % wildcard
The following pattern rule will take any .c file and compile it into a .o file:
Rule can be overridden in makefile
%.o: %.c
$(CC) $(CFLAGS) $(INCLUDES) -c <input> -o <output>
Harry Koehnemann, Computing Studies

14. Another Variable Example
# Variables only – uses defaults! CC=gcc
CFLAGS=-O0
LDFLAGS=-s -L /usr/lib
-- assume nothing up-to-date
$ make SocketExample.o
gcc -O0 -c -o SocketExample.o SocketExample.c
$ make SocketExample
gcc -O0 -s -L . SocketExample.c -o SocketExample
Harry Koehnemann, Computing Studies

15. Interesting Make Arguments
-d print debug information
-f <file> use <file> instead of {mM}akefile
-n list what would be made; do not execute
-t ‘touch’ files to make them up-to-date; do not execute
-e env variables override makefile variables
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16. Harry Koehnemann, Computing Studies
References
GNU make
Harry Koehnemann, Computing Studies