1. On behalf of NatTel we would sincerely like to thank Agilent Technologies Inc. for their valuable support

2. Lets Design a Mixer!
Anurag Nigam

3. Design Target Most important design targets are- Choice of RF
Data Rate &
Bandwidth of the communication system
We have chosen WisAir 531 MAC/BB implementation of wireless USB that allows Ethernet USB Bridge and direct streaming of Internet and Video data on to the network. Data Rates up to 480 Mbps are possible. The radio is implemented using 502 RF Chip. For this system a total bandwidth of 1.7 GHz (3.1 GHz to 4.8 GHz) is used. We plan to alter the frequency band to be slightly higher for the ease of design and also better RF-LO Isolation at 60 GHz. Accordingly we will alter the front end of 502 RF Chip and its LO Frequency. We may not require to do this in later revisions if we expect RF-LO Isolation to be sufficient.
Choice of RF
60 to 67 GHz band is available as license free band. It is oxygen absorption band. It has few advantages-
Due to high absorption by oxygen a smaller micro-cellular layout can be chosen for the network in a cellular broadcast scenario. This allows better spatial frequency reuse and hence higher subscriber capacity.
With smaller size antennas high directivity is possible allowing lower path loss and lower interference.
In case of cellular broadcast, more sectors in a micro-cell can reuse a frequency. This is efficient spectral usage.

4. Design Centering Choice of IF Choice of LO Frequency
Input of a Mixer has a hybrid for RF-LO Isolation. Very small IF will result in poor RF-LO isolation. Similarly, very large IF shall result in gain and phase imbalance at the mixer output due to 10 to 15% bandwidth of the coplanar passive components.
Passive components at best have bandwidth of 30 to 35% of the center-band frequency. Hence, the lower band edge should at least be 1/0.35 times the target bandwidth i.e. 1/0.35 x 1.7 GHz= 4.8 GHz. Then the higher band edge would be =6.5 GHz.
Choice of LO Frequency
We center the design of the input section to be at 60 GHz. IF band is 4.8 GHz-6.5 GHz. Thus 6.5 GHz is centered around 60 GHz.
For this reason, We choose LO frequency to be 57GHz. Choice of LO as 57 GHz establishes the RF band to be 61.8 GHz-63.5 GHz.
Frequency (GHz) 57
61.8
63.5
4.8
6.5 LO RF IF
Figure 1: First Down Conversion

5. Principal of Operation
Signal Flow through the Mixer
LPF
LPF
Figure 2: Equation Based Modeling of Quadrature Mixer
Signal at the output of the Mixer
Balanced Differential Output
The baseband signal around DC is a common mode input to the subsequent differential stages. Hence, it does not show up at the differential output.

6. Circuit Topology 1 2 3 4 5 6 7 CMOS Vcc Bipolar Vcc mm-Wave LO IF1 IF2
Figure 3: Circuit Block Diagram based on the functionality of each block

7. Important Sub-Circuits
Mixer
90˚ Hybrid
50 Ω λ/4 Transmission Line
36 Ω λ/4 Transmission Line
60 GHz Bias De-Coupling
GHz Bias De-Coupling
56 GHz Reflection Stub
60 GHz Input Match
GHz Output Match
Bandgap/PTAT/CTAT Bias 1 2 3 4 5 6 7
Various Important Blocks of the Mixer as per design priority are listed in the figure.
The design is done in 9 exercises. In Exercise 1, 2, 3, 4, 5, 6, 8, 9 & 10 we design sub-circuits.
Exercise 7 is to substitute realistic sub-circuits into the design one by one as we go along Exercises 1 to 10.
Exercise 11 is to simulate complete circuit.
Exercise 12 is to perform the complete Mixer Layout.
Exercise 13 is left as open ended exercise to the participants to craft each sub-circuit as per layout modifications and guarantee the final performance of the Mixer Layout.
Figure 4: Mixer Sub-Circuits

8. Circuit Concepts
Dual Gate FETs have been used for mixers at high frequencies. Issue with such mixers is RF-to-LO isolation. Leakage of RF into Local Oscillator affects Spectral Purity of the Mixer and degrades its IF output in terms of linearity. Leakage of LO to RF can reradiate back into space through the antenna.
To avoid these effects, a 90˚ Hybrid is used at the input of the Mixer. As proposed in Principle of operation, 90˚ & 180˚ delays are expected at the ports 2 and 3, respectively for mm-Wave while same is expected for LO at the ports 3 and 2, respectively. Isolation is expected between ports 1 & 4. 2 3 4 5 6 7
CMOS Vcc
Bipolar Vcc
IF1
IF2 1
mm-Wave LO
In Exercise 1, 2 and 3 we design 90˚ Hybrid at the input of the mixer operating at 60 GHz.
As discussed earlier, 60 GHz is roughly center between LO and RF. 1 2 4 3
Figure 5: 90˚ Hybrid at the input of the Mixer

9. Circuit Concepts
Input matching to the bipolar devices should be a broadband matching covering complete frequency band from 57 GHz to 63.5 GHz.
Input planes, as shown in the figure, should be matched at mm-Wave band and fully miss-matched at IF band. Series Capacitors that miss-match at IF band and couple at mm-Wave band are difficult to design due to their self resonance. 2 3 4 6 7
CMOS Vcc
Bipolar Vcc
IF1
IF2 1
mm-Wave LO 5
Matching Planes
In Exercise 7 we design a narrow band match at the input using ideal lumped components.
In Exercise 8 we design a broadband match to substitute the narrow band match. Layout of input match is carried out, tailored and EM-Simulated.
Figure 6: Input Match to the bipolar devices

10. Circuit Concepts
Output matching to the bipolar devices has to have a bandwidth that is 35% of the center band frequency. It has to be a low pass circuit to reject the higher order mix components. Output Match also has to reflect 57 – 63.5 GHz band by creating a short. Open Circuited Stub marked as 4 in the figure does the same.
Output Match, marked 6 in the figure, can be a single pole match and still be broadband due to low parasitics of the bipolar devices. 2 3 7
CMOS Vcc
Bipolar Vcc
IF1
IF2 1
mm-Wave LO 5 4 6
In Exercise 9 we design low pass match at the output using ideal lumped components.
Ideal lumped components are substituted by Output Match Layout and EM Simulated Components.
The Open Circuited Stub is design in Exercise 6
Figure 7: Output Match to the bipolar devices

11. Circuit Concepts
57 – 63.5 GHz Bias Decoupling has to be broadband. A large bypass MIM capacitor can not be used due to its self resonance in this bias decoupling. Small capacitor can be designed as bypass capacitor or a radial stub can be used for bypass.
4.8 – 6.5 GHz Bias Decoupling has to be broadband. Instead of using a tank circuit, inductor can be designed to be big enough to anti-resonate at 5.65 GHz. 5 4 6 7
CMOS Vcc
Bipolar Vcc
IF1
IF2 1
mm-Wave LO 2 3
62.65 GHz Bias De-Coupling
5.65 GHz Bias De-Coupling
In Exercise 4 we design 57 – 63.5 GHz Bias Decoupling.
In Exercise 5 we design 4.8 – 6.5 GHz Bias Decoupling.
Figure 8: GHz and 5.65 GHz Bias De-coupling Circuits

12. Circuit Concepts
Bias Circuit has two distinct sections- PTAT Current Source and CTAT Voltage Source. The output section of the bias circuit has an Op-Amp Buffer and a Voltage to Current Converter.
In Exercise 10 we design PTAT Current Source, CTAT Voltage Source, Bandgap Module and Voltage to Current Converter. Depending on the across-temperature performance of the mixer, we can tweak appropriate resistors to provide PTAT, CTAT or Bandgap performance. 2 3 4 6
CMOS Vcc
Bipolar Vcc
IF1
IF2 1
mm-Wave LO 5 7
Figure 9: On-Chip Temperature Compensated Bias Circuit

13. Metal Stack for IHP SG25 TM1TM2
TopMetal2
TopVia2
TopMetal1
TopVia1
Metal3
Via2
Metal2
Via1
Metal1
MIM
Figure 10: Metal Stack for IHP Process

14. Substrate Definition in ADS
Step1: Layout Layer Definition Files and Substrate Definition Files are provided by IHP. These files after minor modifications are available in “../ MixerLNATraining /Files” folder in the Training CD.
Copy “IHP_0u25_TM1TM2.lay” into the project root folder and “SG2Hx_TM1TM2_370u.slm” into the “network” folder of the project folder.
Copy to project root folder
Copy to network folder of the project folder
Figure 11: Files provided to setup the Design Project

15. Setting-Up Project
Anurag Nigam

16. New Project Step2: Create New Project “MixerQuad60GHz” as shown below.
Figure 12: Create a New Project, name it and attach a technology file

17. Setup Layers & Substrate Files
Step3: Copy Layout and Substrate Definition Files into proper folders
Figure 14: Substrate Definition File copied to the network folder within the project root folder
Figure 13: Layer Definition File copied to the project root folder in “Users > Default”

18. 90˚ Hybrid Design
Anurag Nigam

19. Ideal Hybrid Design
Step4: Use ideal transmission line components in ADS to design a Hybrid as shown in figure.
λ/4 Electrical Length 1 2 3 4
Establishing Impedances
Establishing Power
Consider for analysis that power is put in port 1 and 4 as Even and Odd Modes with amplitudes +-1/2. Figures 16 and 17 show circuit for Even and Odd Modes. The superimposition will show that power is put only in port 1 while port 4 is matched to characteristic impedance. For simplicity all impedances and terminations are normalized.
Figure 15: Ideal 90˚Hybrid Design
λ/4
λ/8 1
Figure 16: Even Mode Impedances
+1/2
Figure 17: Odd Mode Impedances
λ/4
λ/8 1
+1/2
-1/2

20. ADS Schematic for Ideal Hybrid Simulation
Step5: Create ADS Schematic for Ideal Hybrid simulation. Save the design as “IdealHybrid.dsn”
Figure 18: ADS Schematic for 90˚ Hybrid

21. Simulation Response of Ideal Hybrid
Step6: Plot the S-Parameters as shown in the figure and follow the explanation by the instructor to understand Hybrid Performance
Figure 19: S-Parameter Response of Ideal 90˚ Hybrid

22. Non-50 Ohm Line Design
Step7: Draw the CPWG structure, as shown in the figure, on TopMetal2 and TopMetal1 with proper ground vias on TopVia2 Layer. Rough Dimensions are- 5.2 um wide signal trace with 2.9 um gap to coplanar ground. Total length of the signal trace is roughly 580um. Attach and edit properly the ports for EM simulations. Perform simulations at 60 GHz. Save the layout file as “QuarterLine1_3.dsn”. Refer to the instructor for further details
Figure 21: 3D View of designed 36.6 Ω Line that is electrically λ/4 long
Figure 20: Layout of designed 36.6 Ω Line that is electrically λ/4 long. Proper port definition

23. EM Simulation Response
Step8: Place markers to S11 and S22 traces and normalize them to port impedance
Figure 22: EM Simulation Response of the designed 36.6 Ω CPWG Line

24. Setup to Test Electrical Length
Step9: Setup ADS Schematic as shown in the figure and perform S-Parameter Simulation to determine electrical length of the designed line. Adjust the length to achieve 90˚ Electrical Length. Refer to the Instructor for further details.
Figure 23: S-Parameter Setup to determine electrical length of the designed line

25. 50 Ohm Line Design
Step10: Draw the CPW structure, as shown in the figure, on TopMetal2. Rough Dimensions are- 4 um wide signal trace with 3.3 um gap to coplanar ground. Total length of the signal trace is roughly 580um. Attach and edit properly the ports for EM simulations. Perform EM simulations at 60 GHz. Save the layout file as “QuarterLine2_4.dsn”. Refer to the instructor for further details.
Figure 25: 3D View of designed 50 Ω Line that is electrically λ/4 long
Figure 24: Layout of designed 50 Ω Line that is electrically λ/4 long. Proper port definition

26. EM Simulation Response
Step11: Place markers to S11 and S22 traces and normalize them to port impedance
Figure 26: EM Simulation Response of the designed 50 Ω CPW Line

27. Setup to Test Electrical Length
Step12: Use ADS Schematic earlier implemented to perform S-Parameter Simulation and determine electrical length of the designed line. Adjust the length to achieve 90˚ Electrical Length. Refer to the Instructor for further details.
Figure 27: S-Parameter Setup to determine electrical length of the designed line

28. 90˚ Hybrid Design & Layout
Step13: Copy 36 Ω and 50 Ω lines from previous layouts. Connect them as shown in the figure. Bring out ports using 50 Ω lines. Save the file as “Hybrid60GHz.dsn”.
Figure 28: 3D View of the designed 90˚ Hybrid
Attach and properly define the ports. Perform EM Simulations at 60 GHz. Adjust the dimensions of each branch for optimum performance. Follow the instructor for further details.
Figure 29: Layout of the designed 90˚ Hybrid

29. EM Simulation Response at 60 GHz
Step14: Plot the EM Simulation Response as shown in the figure. Refer to the Instructor for interpretation of the results. In case you are satisfied with the response, simulate the circuit to cover the frequency range of 0 – 228 GHz in order to cover most of the Mix Components.
Figure 30: EM Simulation Response of 90˚ Hybrid at 60 GHz

30. Simulating 90˚Hybrid across frequency
Step15: Setup S-Parameter Simulation Schematic as shown in the figure. Save the file as “TestHybrid.dsn”.
MOM
Instability
Figure 31: EM Simulation Response of 90˚ Hybrid across frequency
This concludes the design of the Hybrid as Input Section of the Mixer

31. 60 GHz Bias Decoupling
Anurag Nigam

32. Role of 60 GHz Bias De-Coupling
Bias Decoupling is used to isolate RF Circuit from the DC Supply current source. For DC, the decoupling looks like a short providing proper DC base current to the active devices while for RF it looks like an open. This allows tuning at the input at the desired frequency.
A short has to be generated for RF on the supply side so that irrespective of the output impedance of the current source, the match at the input does not degrade. Bias Decoupling can take one of the three forms shown below.
Option A
Option B
Option C RF DC
λ/4 RF DC
λ/4 RF DC
Figure 32: Bias Decoupling using lumped components
Figure 33: Bias Decoupling using stubs
Figure 34: Bias Decoupling using mixed components
Option A is not possible at high frequencies due to self resonance of passive components. Option B is best suited for high frequency but occupies large chip area. Option C is slightly degraded in performance but occupies smaller area. We will explore Option B and Option C for our design.

33. Option C- Bias Decoupling @ 57-64 GHz
Step16: Design 0.6pf or smaller (MIM) Capacitor and 50 Ω Quarter-Wavelength long line. Connect them as in the figure. Perform EM Simulations. Alter length for performance. Refer to the instructor for further details. Save the file as “BiasDeCoup60GHz.dsn”. Adjust the cap size and length to maximize decoupling and save the layout as “DeCoup60GHz.dsn”. Re-simulate the circuit to see the improvement.
Figure 35: Bias Decoupling Layout at GHz using mixed components
Figure 36: Bias Decoupling at GHz using mixed components

34. Option C- Bias Decoupling Response
Step17: Plot S11 and S22 for 60 GHz decoupling layout in “BiasDeCoup60GHz.dsn”. Place the markers at the fundamental frequencies i.e. 57 GHz, 61.8 GHz & 63.5 GHz
Figure 37: Response of Bias Decoupling using mixed components at GHz

35. Option C2- Bias Decoupling Response
Step18: Plot S11 and S22 for 60 GHz decoupling layout in “DeCoup60GHz.dsn. Place the markers at the fundamental frequencies i.e. 57 GHz, 61.8 GHz & 63.5 GHz
Figure 38: Response of Bias Decoupling (Optimized) using mixed components at GHz

36. Option B- Bias Decoupling @ 57-64 GHz
Step19: Design Radial Stub to transform ‘Open’ to ‘Short’. Use 50 Ω Quarter-Wavelength long line from previous design to layout the bias decoupling circuit shown in the figure.
Figure 39: Bias Decoupling Layout at GHz using stubs
Figure 40: Bias Decoupling at GHz using stubs

37. Option B- Bias Decoupling Response
Step20: Plot S11, S22 & S21. Place the markers at the fundamental frequencies i.e. 57 GHz, 61.8 GHz & 63.5 GHz
Figure 41: Response of Bias Decoupling using stubs at GHz
This concludes the design of Bias Decoupling at GHz

38. GHz Bias Decoupling
Anurag Nigam

39. Option A- 4.8 – 6.5 GHz Bias Decoupling
Figure 42: Bias Decoupling at 4.8 – 6.5 GHz
Step21: Design a 4.6 pf Capacitor and an inductor large enough to anti-resonate in the desired frequency band of 4.8 – 6.5 GHz. Connect them as shown in the figure. Add ports and edit them appropriately. Perform EM Simulations. For further instructions refer to the instructor. Save the file as “BiasDeCoup3GHz.dsn”
Figure 43: Layout of Bias Decoupling at 4.8 – 6.5 GHz

40. EM Simulation Response of 4.8 – 6.5 GHz Bias Decoupling
Step22: Plot S11, S22 & S21. Place markers at 4.8 GHz & 6.5 GHz
Figure 44: EM Simulation Response of Bias Decoupling at 4.8 – 6.5 GHz
This concludes the design of Bias Decoupling at GHz

41. 56 GHz Reflection Stub at the output
Anurag Nigam

42. 56 GHz Open Circuited Stub Design
Step23: Design a 50 Ω Quarter Wavelength long CPWG 56.5 GHz. Attach the ports and edit them appropriately. Perform EM Simulations. For further details refer to the instructor.
Figure 45: Layout of the Open Circuited Stub at the output of the Mixer
Figure 46: Open Circuited Stub at the output of the Mixer

43. EM Simulation Result of 56 GHz Open Circuited Stub
Step24: Setup S-Parameter Simulation as shown in the figure and perform simulation. Add marker to S11 Trace. Refer to the instructor for explanation.
Figure 47: Response of Open Circuited Stub used to generate short at the 56.5 GHz
This concludes the design of Open Circuited Stub at 56.5 GHz

44. Active Circuit of the Mixer
Anurag Nigam

45. Active Circuit Tuning
Step25: Choose a small HBT device with low parasitics. Bias it at Vcc=1.8V and Ib=26uA. Use EM Simulated Bias Decoupling at input and output and open circuited stub at the output. For broadband input tuning refer to the instructor for tips and tricks. Save the file as “ActiveQuadLeg60_3GHz.dsn”.
EM Simulated Bias Decoupling
Output Match
Broadband Input Match
EM Simulated Open Circuited Stub
Figure 48: Active circuit of the mixer- biased through bias decoupling, matched at input to GHz and at output to GHz

46. Response of Matched Active Stage
Step26: Plot the S-Parameters as shown in the figure. Note that under power matches will change and will have to be retuned.
Figure 49: S-Parameter Simulation Response of the Active circuit

47. Mixer Design & Simulations
Anurag Nigam

48. Mixer Design
Step27: As per the circuit diagram in figure 3, connect the EM Simulated Hybrid and the active circuit designed in the previous section. Generate a symbol for the mixer. Refer to the instructor for details. Save the design as “Mixer60GHzPrelimCoSim.dsn”
Figure 50: Mixer Designed using EM Simulated sections other than input and output matches

49. Across Frequency Simulation of the Mixer
Step28: Setup Harmonic Balance Simulation for the Mixer as shown in the figure. Save the file as “CascodeMix60GHzWithHybridCoSim.dsn”. Refer to the instructor for further details.
Figure 51: Harmonic Balance Simulation Setup to simulate Mixer Response across the frequency band 61.8 – 63.5 GHz.

50. Harmonic Balance Simulation Results
Step29: Write the appropriate equations and plot the results as shown in the figure. Refer to the instructor for details.
Note
Note that the phase imbalance in the input 90˚ Hybrid gets doubled and appears at the output. We started with worst phase imbalance of 3.3˚ in Hybrid and the resulting mixer has imbalance of 6.6˚ at the output. Input tuning and bias decoupling can be used to improve the phase imbalance.
Figure 52: Harmonic Balance Simulation Results across the frequency band 61.8 – 63.5 GHz.

51. Broadband Input Match Design
Anurag Nigam

52. Investigating Input Match
Step30: Setup S-Parameter simulation as in the figure. Lossless Match is Reciprocal. Refer to the instructor for details.
Figure 53: Broadband Input Match
Figure 54: S-Parameter Response of Broadband Input Match

53. Input Match
Step31: Input Match has loss and hence can not be reciprocal. This means that there will be mismatch losses at both the interface planes. To construct the match refer to the instructor and the next slide. Save the layout file as “IPLoad1.dsn”.
Figure 56: Broadband Input Match at GHz
Figure 55: Layout of Broadband Input Match

54. Building Input Match
Step32: Design and EM Simulate one by one each passive component of the input match. Save the file as “InputMatchBuildUp.dsn”. Refer to the instructor for more information. 1 2 3 4 1 2 3 4 3 1 4 2
Figure 57: Buildup of Broadband Input Match at GHz

55. EM Simulation Response of the Input Match
Step33:
EM Simulation Response of the Input Match showing mismatch losses at 50 Ω and (7.495+j*7.290) Ω Plains and the overall loss of the match
Ideal
Layout
Figure 58: EM Simulation Response of the Input Match at GHz

56. Verify Input Match and Adjust Load
Step34: Replace the EM Simulated Input Match in the Active Circuit Tuning Simulations as shown below and readjust the output Match. Save the design as “ActiveQuadLeg60_3GHz2.dsn”.
Figure 59: Active Circuit retuned at the Output for band centering

57. Results from Active Circuit Tuning
Step35: Plot the response of the Design in “ActiveQuadLeg60_3GHz2.dsn” centered across the band.
Figure 60: Response of the Active Circuit, retuned at the Output for band centering

58. Second Variation of Bias Decoupling & Input Match
Step36: Save the Design “ActiveQuadLeg60_3GHz2.dsn” as “ActiveQuadLeg60_3GHz3.dsn”. Change the Bias Decoupling at the input to “OptionC2” which is better matched for LO Frequency. This will drastically improve Conversion Gain of the Mixer. This will require retuning of the Input Match & the Output Match. Refer to the next slide and the instructor for details.
Figure 61: Input Match retuned with “Option C2” Bias Decoupling at the Input

59. Results from Active Circuit Tuning
Step37: Plot the response of the Design in “ActiveQuadLeg60_3GHz3.dsn”.
Improved I/P Match
Figure 62: Response of the Active Circuit, with “OptionC2” as Bias Decoupling at the input and retuned Input and Output Matches

60. New Active Circuit in Mixer Schematic
Step38: Replace the Active Circuit in the Mixer with the circuit from
“ActiveQuadLeg60_3GHz3.dsn”. Rename the design file as “Mixer60GHzPrelimCoSim3.dsn”. Adjust the base current to HBT devices to be 32 μA. For further details refer to the instructor.
Figure 63: Updated Mixer Circuit Schematic

61. Response of the Updated Mixer
Step39: Plot the response of the mixer as shown in the figure. Figure 52 shows response of the mixer using ideal input match. Figure 58 shows loss in the input match. This figure shows a loss of dB in broadband input match.
Figure 64: Simulation Response of the mixer with EM Simulated I/P Match

62. Output Match Design
Anurag Nigam

63. Investigating Output Match
Step40: Setup S-Parameter simulation as in the figure. Lossless Match is Reciprocal. Separately Design Inductor and Capacitor and connect them in series to construct the load. EM Simulate the Load Match. Refer to the instructor for further details.
Figure 65: Output Match
Figure 66: S-Parameter Response of the Output Match

64. Building Output Match
Step41: Design 3 pf MIM Capacitor. Save the file as “Cap3pf.dsn”. Design 1.8 nH Inductor. Save the file as “Ind1_8nH.dsn”. Connect them in series as shown in the figure. Add ports and define their properties appropriately. EM Simulate the Output Load Match.
Figure 67: Output Match Layout
Figure 68: Output Match at 4.8 – 6.5 GHz

65. Mixer with EM Simulated Components
Step42: Replace the output match in “Mixer60GHzPrelimCoSim3.dsn” with EM Simulated Output Match. Save the Design as “Mixer60GHzPrelimCoSim4.dsn”.
Figure 69: Mixer with all EM Simulated Components

66. Mixer Response
Step43: Replace “Mixer60GHzPrelimCoSim3” by “Mixer60GHzPrelimCoSim4” in “CascodeMix60GHzWithHybridCoSim.dsn”. Perform
Harmonic Balance Simulations. Plot the results as shown in the figure. Refer to the instructor for further details.
Figure 70: Across Frequency Simulation Response of the Mixer

67. Bias Circuit Design
Anurag Nigam

68. Bi-CMOS Bandgap Bias Circuit Overview
Bandgap Bias Circuit Basics
Bandgap bias circuit consists on two circuits with alternate performances across the temperature. These are- “PTAT (Proportional To Absolute Temperature” Current Reference and CTAT “Complementary to PTAT” Voltage Reference. If PTAT Current is sourced into the CTAT Voltage Reference then the voltage across the CTAT is fairly constant across temperature for large temperature range.
Output Buffer Circuit is essential part of the bias circuit that converts Bandgap Voltage Reference to Current Source. The Current Source is able to maintain constant current across temperature irrespective of the voltage across the source.
Step44: Design the PTAT Current Source as explained in BiCMOS Circuit Design Workshop
Bandgap Current Source
PTAT
CTAT
Output Buffer
β-Helper
Start-up Circuit
Figure 71: Bandgap referenced Current Source
Figure 72: PTAT Current Source with Start-up Circuit and β-Helper

69. CTAT & Bandgap Voltage Reference Design
Step45: From PTAT Current Source performance, determine CTAT design as explained in BiCMOS Circuit Design Workshop. Connect PTAT Current Source and CTAT Voltage Reference to design Bandgap Voltage Reference. For further details refer to the instructor.
Figure 73: PTAT Current Source Performance across Temperature
Figure 74: CTAT Voltage Reference Circuit Design

70. Bandgap Voltage Reference Performance
Step46: Perform across temperature DC Simulation of the Bandgap Voltage Reference. Plot the results as shown in the figure. Refer to the instructor for further details.
Figure 75: Bandgap Voltage Reference Circuit Design
Figure 76: Bandgap Performance

71. Output Buffer & Voltage to Current Converter Design
Step47: Design a Voltage to Current Converter using an Op-Amp and mirror appropriate current to the output i.e. 34 μA by sizing the output current mirror devices. Op-Amp is a simple differential stage. Refer to the instructor for further details.
Figure 77: Voltage to Current Converter & Output Buffer Circuit

72. Output Buffer & Output Stage Performance
Step48: Figure shows the design of a simple differential stage used as an Op-Amp. Perform across temperature DC Simulation of the circuit shown in previous slide. Plot across temperature DC Simulation Response of the Output Stage as shown in the figure. Refer to the instructor for explanation.
Figure 78: Differential Amplifier Circuit
Figure 79: Across temperature response of the output stage

73. Complete Bandgap Current Source
Step49: Connect all the three sections of the Bandgap Current Source as shown in the figure. Perform DC Simulations across temperature. Note that the circuit can be skewed to give slight PTAT or CTAT performance also depending on real across temperature performance of the mixer.
Figure 80: Complete Bandgap Referenced Current Source

74. Across Temperature Response of the Current Source
Step50: Plot the output currents Vs temperature from the Bandgap Referenced Current Source shown in the previous slide. Layout the bias circuit as shown in the figure as per the space constraints.
Figure 81: Layout of the bias circuit
Figure 82: Across temperature response of the bias circuit

75. Final Mixer Design & Layout
Anurag Nigam

76. HB Simulation of the Mixer
Step51: Connect the bias circuit in the schematic “CascodeMix60GHzWithHybridCoSim.dsn” as shown in the figure and save the file.
Figure 83: Across frequency Harmonic Balance Simulation of Mixer

77. Across frequency HB Simulation Response
Step52: Perform HB Simulation across frequency band 61.8 – 63.5 GHz with LO power in tune mode. Refer to the instructor for details.
Figure 84: Across frequency Harmonic Balance Simulation Response of the Mixer with varying LO Power

78. Across Power HB Simulation Response
Step53: Modify “CascodeMix60GHzWithHybridCoSim.dsn” for across input power HB Simulation at the center band frequency of GHz. Save the file as “CascodeMix60GHzWithHybridCoSimAccPwr.dsn”. Refer to the instructor for details.
Figure 85: Across input power Harmonic Balance Simulation Response of the Mixer

79. Mixer Layout
Step54: Use all the layouts of components designed till now in this exercise. Position, align and in case not fitting modify them to fit and connect them as per the designed mixer circuit. Add pads from the library in the formation so as to be able to use Cascade Infinity “GSGSG” Probes and DC Probes for all the electrical contacts external to the circuit. Add Chip Ring as recommended by the Fab.
Figure 86: Approximate Mixer Layout