1. Clock Skew and Slow Control Register issues
Frédéric DULUCQ
12/02/2008

2. Frederic DULUCQ - dulucq@lal.in2p3.fr
Clock Skew Definition
Definition : Differences in clock signal arrival times across the chip
12/02/2008
Frederic DULUCQ -

3. Frederic DULUCQ - dulucq@lal.in2p3.fr
Possible problem 1
Difference between data and clock routing delay
Consequence : need only 1 clock edge instead of 2 to shift data
 like only 1 flip flop (ghost FF)
12/02/2008
Frederic DULUCQ -

4. Frederic DULUCQ - dulucq@lal.in2p3.fr
Possible problem 2
Difference between data and clock routing delay + load
With 320pF DFC1 : C Q Rise : 2.30 ns
C Q Fall : 1.80 ns
More difference with QN (1.80 and 2.60 ns)
Consequence : ‘1’ can not go through slow control.
 Need several ‘1’
12/02/2008
Frederic DULUCQ -

5. First order timing analysis
OK if :
tCKQ2 < tCQ1 + tRDQ1 -tHOLD2
 Delay on data must be ≥ Clock Skew - K
tCKQ2 : Clock Skew (routing delay)
tCQ1 : C  Q timing (techno dependant) : 0.4 to 2.60 ns
tRDQ1 : Routind delay on data path
tHOLD2 : D  C timing (techno dependant) : about 0.1 ns
Clock must arrive to 2nd FF before data changing on D2
12/02/2008
Frederic DULUCQ -

6. Frederic DULUCQ - dulucq@lal.in2p3.fr
Clock reversing
Clock must arrive before data so  clock from end to begin A B
To do inside and outside the ASIC (chip to chip) : clock follows data path (routing rule).
12/02/2008
Frederic DULUCQ -

7. Alternative edge clocking
Use 2 FF for 1 Slow Control bit. Rising edge capture data and falling edge send it to next FF. A B C D
No routing rules : if not working  slow the clock to increase margin = half period (OK for chip to chip timing).
12/02/2008
Frederic DULUCQ -

8. Frederic DULUCQ - dulucq@lal.in2p3.fr
Discussion
Alternative clock edges  safest
Add extra “falling edge FF” before long wire or load
Mix 2 solutions
Post layout simulation of SC
In digital low skew clock is made by clock tree
Others
12/02/2008
Frederic DULUCQ -