1. August 2004
doc.: IEEE / n
August 2004
Project: IEEE P Working Group for Wireless Local Area Networks (WLANs)
Submission Title: [STMicroelectronics LDPCC Proposal for n CFP]
Date Submitted: [13 August 2004]
Source: [Nicola Moschini, Massimiliano Siti, Stefano Valle - Andres Vila Casado, Prof. Richard Wesel]
Company [STMicroelectronics, N.V.] [University of California at Los Angeles]
Address [Via C. Olivetti, 2, Agrate Brianza, Italy] [405 Hilgard Avenue, Los Angeles CA]
Voice: [ ], FAX: [ ]
[{Nicola.Moschini, Massimiliano.Siti,
Re: [This submission presents the proposal for optional advanced coding of STMicroelectronics to the n Call For Proposals (Doc #11-03/0858r5) that was issued on 17 May 2004]
Abstract: [This presentation details STMicroelectronics’ LDPCC partial proposal for IEEE TGn. Rate-compatible LDPCCs are presented as optional advanced coding technique, in order to achieve a higher coverage and/or throughput in MIMO-OFDM systems. ]
Purpose: [STMicroelectronics offers this contribution to the IEEE n task group for its consideration as the solution for standardization.]
Notice: This document has been prepared to assist the IEEE P It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein.
Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P
N. Moschini, M. Siti, S. Valle, STMicroelectronics
N. Moschini, M. Siti, S. Valle, STMicroelectronics

2. August 2004
Outline
Reasons for introducing an optional advanced coding technique in n.
Reasons for preferring Low Density Parity Check Codes (LDPCC).
Variable-rate LDPCC proposal:
principle
performance
complexity
N. Moschini, M. Siti, S. Valle, STMicroelectronics

3. Reasons for advanced coding techniques in .11n
August 2004
Reasons for advanced coding techniques in .11n
Advanced coding techniques significantly boost performance in MIMO-OFDM systems  increase in the range and/or the throughput of the system.
Advanced coding techniques, like LDPCC or turbo codes, rely upon iterative decoding: as technology improves ( more iterations) the coding gain can potentially improve.
N. Moschini, M. Siti, S. Valle, STMicroelectronics

4. Targets for advanced coding in 11n
August 2004
Targets for advanced coding in 11n
Code rate flexibility
1/2, 2/3, 3/4, 5/6
Codeword flexibility
range bit
SNR gain compared to CC k=7
> 2dB
Max Throughput
~540Mbps
Latency
< 6us
Complexity
< 800kgates
N. Moschini, M. Siti, S. Valle, STMicroelectronics

5. Motivation for promoting LDPCC as optional advanced coding technique
August 2004
Motivation for promoting LDPCC as optional advanced coding technique
Performance is significantly better than 64-state CC [1].
LDPCC are intrinsically more parallelizable than other codes.
LDPCC can be designed to have good performance at every rate (i.e. avoiding puncturing or shortening) without exploding HW complexity.
LDPCC performances have been demonstrated with 12 iterations: technology evolution will make feasible a larger number of iterations providing further gains.
The LDPCC class described in this proposal [2] is the optional advanced coding technique in the WWISE complete proposal [3].
N. Moschini, M. Siti, S. Valle, STMicroelectronics

6. Proposal: a variable-rate structured LDPCC
August 2004
doc.: IEEE / n
August 2004
Proposal: a variable-rate structured LDPCC
The performance of different matrices show, in general, slight differences for short block lengths.
Implementation complexity is a key factor.
Structured parity check matrices allow a higher degree of decoder parallelization compared to random matrix design.
Rate-compatibility, i.e. good performance at every rate while avoiding puncturing or shortening, is essential.
A common shared HW architecture for all the rates and all the codeword lengths ensures low cost devices.
N. Moschini, M. Siti, S. Valle, STMicroelectronics
N. Moschini, M. Siti, S. Valle, STMicroelectronics

7. Structure of Rate-1/2 “mother” LDPC matrix(1/2)
August 2004
Structure of Rate-1/2 “mother” LDPC matrix(1/2)
ZERO MATRIX
STRUCTURED MATRIX
BI-DIAGONAL MATRIX
For efficient implementation, red squares are super-positions of cyclic permutations of the identity matrix.
Linear-complexity encoder based on back substitution thanks to the block-lower triangular structure.
Matrices for different code sizes are different, but all share the structure described in these two slides.
N. Moschini, M. Siti, S. Valle, STMicroelectronics

8. Structure of Rate-1/2 “mother” LDPC matrix(2/2)
August 2004
Structure of Rate-1/2 “mother” LDPC matrix(2/2)
H is divided into p x p (p=27) sub-matrices that are either the all-zero matrix or a superposition of cyclic permutations of identity matrix as:
S0=
S3=
S7=
The green block represents a bi-diagonal sub-matrix in order to avoid having p degree one variable nodes
N. Moschini, M. Siti, S. Valle, STMicroelectronics

9. Variable-rate LDPC through row-combining
August 2004
doc.: IEEE / n
August 2004
Variable-rate LDPC through row-combining
Combining rows of the parity-check matrix (H) for the lowest rate code (“mother code”) produces H for higher rates.
This is equivalent to replacing a group of check nodes with a single check node that sums all the edges coming into each of the original check nodes.
N. Moschini, M. Siti, S. Valle, STMicroelectronics
N. Moschini, M. Siti, S. Valle, STMicroelectronics

10. Variable-rate matrices design criteria
August 2004
Variable-rate matrices design criteria
Row-combining of rows which do not have a ‘1’ in the same position  the same variable node degree distribution for all rates.
The selection of rows to sum preserves the lower triangular structure throughout all the rates.
In addition, the codes are designed to avoid length 4 cycles and also to have a good performance in the error floor region [4][5].
N. Moschini, M. Siti, S. Valle, STMicroelectronics

11. Row combining example (1/4)
August 2004
Row combining example (1/4)
Rate ½
Rate-1/2 Mother LDPC Matrix
N. Moschini, M. Siti, S. Valle, STMicroelectronics

12. Row combining example (2/4)
August 2004
Row combining example (2/4)
Rate ¾
Rate ½
Combining two rows produces rate-3/4
N. Moschini, M. Siti, S. Valle, STMicroelectronics

13. Row combining example (3/4)
August 2004
Row combining example (3/4)
Rate 5/6
Rate ½
Three at a time produces
rate-5/6
N. Moschini, M. Siti, S. Valle, STMicroelectronics

14. Row combining example (4/4)
August 2004
Row combining example (4/4)
Rate 2/3
Rate ½
Variable grouping produces
rate-2/3
N. Moschini, M. Siti, S. Valle, STMicroelectronics

15. Advantages of Variable-rate structured LDPC
August 2004
Advantages of Variable-rate structured LDPC
A new method to design LDPCC for a variety of different code rates that all share the same fundamental decoder architecture.
An important advantage of this approach is that all code rates have the same block length (a key performance factor) and the same variable degree distribution (an important code property).
Low-complexity encoding (because of block-lower triangular structure) is preserved for all the code rates.
Different ‘mother’ parity-check matrices, to provide different block sizes, can be added at the expense of small extra-HW complexity (basically, ROM for matrix storage).
Other approaches (i.e. puncturing and shortening) suffer from performance degradation.
N. Moschini, M. Siti, S. Valle, STMicroelectronics

16. August 2004
doc.: IEEE / n
August 2004
LDPCC parameters
Codeword size
1944, 1296, 648 bits
Code rate flexibility
1/2, 2/3, 3/4, 5/6
Codeword lengths are selected in order to minimize the padding bits of OFDM-MIMO symbols. Lengths are searched among the multiples of the number of coded bits per OFDM-MIMO symbol.
Here 54 data carriers for OFDM symbols are assumed.
The present proposal holds with minor changes in case of a different number of data carriers (e.g. 48).
N. Moschini, M. Siti, S. Valle, STMicroelectronics
N. Moschini, M. Siti, S. Valle, STMicroelectronics

17. Performance in AWGN channel & BPSK
August 2004
Performance in AWGN channel & BPSK 1
1.5 2
2.5 3
3.5 4
4.5 10 -4 -3 -2 -1 E b /N
FER
LDPCC Iterations
Rate 1/2
Rate 2/3
Rate 3/4
Rate 5/6
N. Moschini, M. Siti, S. Valle, STMicroelectronics

18. Performance in MIMO channels (1/7)
August 2004
Performance in MIMO channels (1/7)
Simulation conditions
Packet
Size
1000 bytes
# of OFDM data carriers 54
TGn Channel Model [6]
Model
B-NLOS, D-NLOS, Fourier
Tx x Rx Antenna
2x2, 2x3
Antenna spacing
0.5
LDPCC
Decoding Algorithm
BCJR
# Iterations 12
Matrices
rate-compatible
Codeword
1944,1296,648
Receiver
Channel est. & synchr.
Real
MIMO Detector
MMSE
N. Moschini, M. Siti, S. Valle, STMicroelectronics

19. Performance in MIMO channels (2/7)
August 2004
Performance in MIMO channels (2/7) 6 8 10 12 14 16 18 20 -3 -2 -1
SNR [dB]
PER
16QAM, R=1/2
16QAM, R=3/4
64QAM, R=2/3
64QAM, R=3/4
64QAM, R=5/6
CC59: 20 MHz, 2x2, Fourier Channel, 1944 LDPCC (12 Iterations)
N. Moschini, M. Siti, S. Valle, STMicroelectronics

20. Performance in MIMO channels (3/7)
August 2004
Performance in MIMO channels (3/7) 10 15 20 25 30 35 40 45 -3 -2 -1
SNR [dB]
PER
CC67: 20 MHz, 2x2, Channel B NLOS, LDPCC 1944 (12 Iterations) vs. BCC K7 - solid line LDPCC
16QAM, R=1/2
16QAM, R=3/4
64QAM, R=2/3
64QAM, R=3/4
64QAM, R=5/6
N. Moschini, M. Siti, S. Valle, STMicroelectronics

21. Performance in MIMO channels (4/7)
August 2004
Performance in MIMO channels (4/7) 5 10 15 20 25 30 35 40 -3 -2 -1
SNR [dB]
PER
CC67: 20 MHz, 2x3, Channel B NLOS, LDPCC 1944 (12 Iterations) vs. BCC K7. - solid line LDPCC
16QAM, R=1/2
16QAM, R=3/4
64QAM, R=2/3
64QAM, R=3/4
64QAM, R=5/6
N. Moschini, M. Siti, S. Valle, STMicroelectronics

22. Performance in MIMO channels (5/7)
August 2004
Performance in MIMO channels (5/7) 10 15 20 25 30 35 40 45 -3 -2 -1
SNR [dB]
PER
CC67: 20 MHz, 2x2, Channel D NLOS, LDPCC 1944 (12 Iterations) vs. BCC K7 - solid lines LDPCC
16QAM 1/2
16QAM 3/4
64QAM 2/3
64QAM 3/4
64QAM 5/6
N. Moschini, M. Siti, S. Valle, STMicroelectronics

23. Performance in MIMO channels (6/7)
August 2004
Performance in MIMO channels (6/7) 10 15 20 25 30 35 -4 -3 -2 -1
SNR [dB]
PER
16QAM 1/2
16QAM 3/4
64QAM 2/3
64QAM 3/4
64QAM 5/6
CC67: 20 MHz, 2x3, Channel D NLOS, LDPCC 1944 (12 Iterations) vs. BCC K7 - solid lines LDPCC
N. Moschini, M. Siti, S. Valle, STMicroelectronics

24. Performance in MIMO channels (7/7)
August 2004
Performance in MIMO channels (7/7) 10 15 20 25 30 35 40 -3 -2 -1
SNR [dB]
PER
Comparison: LDPCC (12 Iterations), BCC, 20 MHz, 2x3, Channel B NLOS
BCC 16QAM, R=1/2
LDPCC 16QAM, N=648, R=1/2
LDPCC 16QAM, N=1296, R=1/2
LDPCC 16QAM, N=1944, R=1/2
BCC 64QAM, R=5/6
LDPCC 64QAM, N=648, R=5/6
LDPCC 64QAM, N=1296, R=5/6
LDPCC 64QAM, N=1944, R=5/6
N. Moschini, M. Siti, S. Valle, STMicroelectronics

25. PSDU transmission
August 2004
(k, n) LDPC code and generic PSDU length result in an integer number of LDPCC frames plus a last shorter frame of size [(n – k)+ k1] ≤ n, where k1 is the number of last information bits.
Information bits of the last frame are padded with zeros for encoding  fixed number of parity bits equal to p = (n – k).
The padded bits are not transmitted (i.e. shortening).
The last frame requires fewer iterations (see next slides) because it is more protected:
N. Moschini, M. Siti, S. Valle, STMicroelectronics

26. Results on zero-padding (1/2)
August 2004
Results on zero-padding (1/2) 10
Zero-padding half the information bits in 1944
Rate = 2/3 -1 10
FER -2 10
N=1944, Rate=2/3, 12 iterations
N=1296, Rate=1/2, 6 iterations
N=1296, Rate=1/2, 7 iterations -3 10
2.5 3
3.5 4
4.5 E /N s
N. Moschini, M. Siti, S. Valle, STMicroelectronics

27. Results on zero-padding (2/2)
August 2004
Results on zero-padding (2/2) 10
Zero-padding half the information bits in 1944
Rate = 5/6 -1 10 -2 10
FER -3 10
N=1944, Rate=5/6, 12 iterations
N=1134, Rate=5/7, 5 iterations
N=1134, Rate=5/7, 6 iterations -4 10
4.5 5
5.5 6
6.5 E s /N
N. Moschini, M. Siti, S. Valle, STMicroelectronics

28. Var-Rate LDPCC: implementation complexity
August 2004
Var-Rate LDPCC: implementation complexity
Massive HW re-use is possible because all the rates are derived from the “mother” rate ½ and the same sub-matrix size is adopted for all the codeword lengths.
The encoder has a linear complexity thanks to its lower triangular structure that permits the back substitution.
A different mother matrix for each code size implies extra-ROM, as the use of the same structure for the basic building blocks (27x27) allows efficient re-use of parallel processors.
Main targets in the table can be met.
Area (Max)
800k gates
Iterations 12
Decoder
Freq. (Max)
240 MHz
Decoding
Latency
6 us
N. Moschini, M. Siti, S. Valle, STMicroelectronics

29. August 2004
doc.: IEEE / n
August 2004
Conclusions
This proposal contains LDPCC designed with a powerful/well performing technique to generate variable rate codes up to rate 5/6.
Performances are significantly better than 64-state CC (>= 10-2 PER for all code rates higher than 1/2).
In order to optimize padding management and/or handle short packets, different code-size matrices have been designed; they can coexist at low extra HW complexity and yield similar performances.
These codes result in a reasonable overall complexity / latency / performance trade-off.
Results have been obtained with 12 iterations: technology evolution will make feasible a larger number of iterations providing further gains.
N. Moschini, M. Siti, S. Valle, STMicroelectronics
N. Moschini, M. Siti, S. Valle, STMicroelectronics

30. August 2004
References
[1] IEEE Std a-1999, “Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specification: high speed physical layer in the 5 GHz band”, IEE-SA Standards Board ( )
[2] IEEE / n, “STMicroelectronics Partial Proposal for LDPCC as optional coding technique for IEEE TGn High Throughput Standard”, N. Moschini, M. Siti, S.Valle, et al.
[3] IEEE / n, “WWiSE group PHY and MAC specification,” M. Singh, B. Edwards et al.
[4] Tian T., Jones C., Villasenor J. D. and Wesel R. D., "Selective Avoidance of Cycles in Irregular LDPC Code Construction," IEEE Transactions on Communications, August 2004.
[5] Ramamoorthy A. and Wesel R. D., "Construction of Short Block Length Irregular LDPC Codes,", in Proc. IEEE ICC 2004, Paris, France, June 2004.
[6] IEEE /940r1, "IEEE P802.11, Wireless LANs - TGn Channel Models" - January 9, 2004
N. Moschini, M. Siti, S. Valle, STMicroelectronics