1. Markus Friedl (HEPHY Vienna)
B2GM, 23 July 2012
Front-End & FADC
Markus Friedl (HEPHY Vienna)

2. Readout Chain Overview
Analog APV25 readout is through copper cable to FADCs
Junction box provides LV to front-end
1748 APV25 chips
Front-end hybrids
Rad-hard DC/DC converters
Analog level translation, data sparsification and hit time reconstruction
Unified Belle II DAQ system
~2m copper cable
Junction box
~10m copper
cable
FADC+PROC
Unified optical data link (>20m)
Finesse Transmitter
Board (FTB)
COPPER
M.Friedl (HEPHY Vienna): Front-End & FADC
23 July 2012

3. Front-End: New Hybrids
New hybrids for L4,5,6 (forward side)
Geometry, connector, mounting holes, chip positions according to overall SVD design
2 variants:
P-side: 4 APV25 chips
N-side: 6 APV25 chips
Tested OK with chips
Soon to be used for modules with sensors
M.Friedl (HEPHY Vienna): Front-End & FADC
23 July 2012

4. Front-End: Hybrid Arrangement
2 hybrid boards (each 0.7mm thick) will be put together back-2-back (electrically isolated) and cooled from one side
Vias underneath APV25 chips will transfer heat to other side
To be tested and optimized…
M.Friedl (HEPHY Vienna): Front-End & FADC
23 July 2012

5. Junction Box: Mother Board
Junction box board with DC/DC converters to be placed in SVD DOCK boxes
1 and 2 bare hybrid boards (without sensors) attached for tests with 2m final cable
M.Friedl (HEPHY Vienna): Front-End & FADC
23 July 2012

6. DC/DC Converter: Noise Comparison
Test hybrid
(larger)
Belle II design (smaller)
Same noise within measurement precision (few %) between conventional and DC/DC powering!
M.Friedl (HEPHY Vienna): Front-End & FADC
23 July 2012

7. Junction Box: DOCK Design
DOCK box contains 6 mother boards
Shape will be similar to SVD2 DOCKs, but smaller and lighter to leave some space for shielding
Detail design in progress
M.Friedl (HEPHY Vienna): Front-End & FADC
23 July 2012

8. Junction Box: DOCK Draft Design
(Top lid not shown)
Construction similar to SVD2 case
Mostly aluminum, only bottom plate copper (to be cooled)
M.Friedl (HEPHY Vienna): Front-End & FADC
23 July 2012

9. Junction Box: DOCK Arrangement
SVD
PXD
Backward
Forward
Space for shielding
(PXD box is only a placeholder)
M.Friedl (HEPHY Vienna): Front-End & FADC
23 July 2012

10. Readout Electronics: Scheme
No direct connection between power supplies and FADC
Bias currents are measured remotely by FADC
M.Friedl (HEPHY Vienna): Front-End & FADC
23 July 2012

11. FADC: Overall Concept
Similar to SVD2 FADC, but with higher density (48 APV25 inputs) and more powerful FPGA
M.Friedl (HEPHY Vienna): Front-End & FADC
23 July 2012

12. FADC: Level Translation Daughter Boards
Analog board: existing design, but simplified
Digital board: completely new design based on digital isolator ICs (Analog Devices)
No floating LV power needed for either board!
M.Friedl (HEPHY Vienna): Front-End & FADC
23 July 2012

13. FADC: Level Translation Tests
APV25 Hybrid
Ana+Digi daughter boards on adapter board
APVDAQ Repeater
Both boards tested thoroughly, working perfectly fine 
Short (2m) and long (12m) cable to FADC
100V between floating and GND sides
No damage with repeated instantaneous shorting of HV
M.Friedl (HEPHY Vienna): Front-End & FADC
23 July 2012

14. FADC: Other Parts Still in design
Several parts already designed and verified
Often re-using circuits from other projects
Example: bias current monitoring works very well with multi-channel 24bit  ADC intended for thermocouple readout
M.Friedl (HEPHY Vienna): Front-End & FADC
23 July 2012

15. FADC: Central Intelligence
Altera Stratix 4GX (EP4SGX180KF40C2N)
1517 pins (744 I/O) BGA
88 high-speed SERDES (48 needed for FADCs)
Already purchased 3 devices (at 4k€ each)
Now finding suitable connectors and designing daughter board
Basic firmware exists in present FADC prototype
Will be converted and extended once hardware finished
M.Friedl (HEPHY Vienna): Front-End & FADC
23 July 2012

16. Summary & Outlook Front-end: Junction box: FADC:
new hybrids – working fine 
Junction box:
DC/DC converters – working fine, no noise penalty 
DOCK box to be designed
FADC:
Level translation daughter boards – working fine 
Other parts in progress
Firmware to be done once hardware is ready
M.Friedl (HEPHY Vienna): Front-End & FADC
23 July 2012