1. Chapter 7 Designing Sequential Logic Circuits Rev 1.0: 05/11/03
1.1: 5/23/03

2. Sequential Logic Finite State Machine (FSM) Pipelined System
2 storage mechanisms:
Positive feedback (SRAM)
Charge-based (DRAM)

3. Naming Conventions In our textbook:
a latch is Level-sensitive flip-flop
a register is Edge-triggered flip-flop
There are many different naming conventions
For instance, many books call Edge-triggered elements flip-flops (asynchronous JK, SR)  This leads to confusion

4. Latch v.s. Register Latch stores data when clock is low (or high)
stores data when clock rises (on edges) D Q D Q
Clk
Clk
Clk
Clk D D Q Q

5. Latches
transparent
hold
hold
hold

6. Latch-Based Design N latch is transparent when f = 0; hold when f = 1
P latch is transparent when f = 1; hold when f = 0 f f N P
Logic
Latch
Latch
Logic

7. Timing Definitions t
CLK D c - q
hold su Q
DATA
STABLE
Register
CLK D Q
(a) Setup time (T_su): the time before the clock edge that the D input has to be stable
(b) Hold time (T_hold): the time after tue clock edge that the D input has to main stable
(c) Clock-to-Q delay (Tc-q): the delay from the positive clock input to the new value of the Q output.

8. Characterizing TimingD -Q D Q D Q
Clk
Clk t t C -Q C -Q
Register
Latch

9. Maximum Clock FrequencyT
CLK
tclk-Q + tp,comb + tsetup
Also:
tcdreg + tcdlogic >= thold
tcd:
Contamination Delay
= Minimum delay
tclk-Q + tp,comb + tsetup <= T

10. Mux-Based Latches Negative latch (transparent when CLK= 0)
Positive latch
(transparent when CLK= 1)
CLK 1 D Q 1 D Q
CLK

11. Mux-Based Latch

12. Mux-Based Latch NMOS only Non-overlapping clocks CLK Q CLK Q CLK CLK M

13. Writing into a Static Latch
Use the clock as a decoupling signal, that distinguishes between the transparent and opaque states D
CLK
Forcing the state
(can implement as NMOS-only)
Converting into a MUX

14. Master-Slave (Edge-Triggered) Register
Two opposite latches trigger on edge
Also called master-slave latch pair

15. Master-Slave Register
Multiplexer-based latch pair Q M D
CLK T 2 I 1 3 4 5 6

16. Setup Time
I2-T2 : I2 output to T2

17. Clk-Q Delay Volts 2.5 CLK 1.5 D t t Q 0.5 2 0.5 0.5 1 1.5 2 2.5
- q(lh) t
Volts c
- q(hl) Q
0.5 2
0.5
0.5 1
1.5 2
2.5
time, nsec

18. Reduced Clock Load Master-Slave Register
c.f: 8 Clock loads in Mater-Slave Register Design

19. Avoiding Clock OverlapX
CLK
CLK Q A D B
CLK
CLK
(a) Schematic diagram
CLK
CLK
(b) Overlapping clock pairs

20. SR Flip-Flop: Cross-Coupled Pairs
Cross-coupled NORs
NOR-based Set-Reset
Flop-Flop

21. Cross-Coupled NAND Cross-coupled NANDs Added Clock Control
This asynchronous SR FF
is not used in datapaths any more, but is a basic building memory cell

22. Output voltage dependence on transistor width
Sizing Issues
Output voltage dependence on transistor width
Transient response

23. Storage Mechanisms
Static
Dynamic (charge-based) D
CLK Q

24. Clock Overlap
T0-0: T1 and T2 on
 Race Condition

25. Making a Dynamic Latch Pseudo-Static
Adding a weak feedback inverter

26. Clocked CMOS (C2MOS)
Clock 1
Master
Evaluate
Hold
Slave
High-impedance: Hold
Output
Previous value stored in CL2
New Value of CL1
“Keepers” can be added to make circuit pseudo-static

27. Insensitive to Clock-OverlapDD DD DD DD M M M M 2 6 2 6 M M 4 8 X X D Q D Q 1 M 1 M 3 7 M M M M 1 5 1 5
(a) (0-0) overlap
(b) (1-1) overlap

28. True Single-Phase Clocked Register (TSPC)
Positive latch
(transparent when CLK= 1)
Negative latch
(transparent when CLK= 0)
A register can be constructed by cascading Positive and
Negative Latches  12 transistors are used!

29. Including Logic in TSPC
Example: logic inside the latch
AND latch

30. Positive Edge-triggered Register in TSPC

31. Pipelining
Reference
Pipelined

32. Pipelining At the expense of “Latency (input-to-output delay)”
 Not good for interactive communicaitons

33. Latch-Based Pipeline

34. 7.5.2. NORA CMOS- A logic style for pipelined structure
(To be added next time)