1. Interfacing with Hardware

2. I/O Devices Two primary aspects of computer system
Processing (CPU + Memory)
Input/Output
Role of Operating System
Provide a consistent interface
Simplify access to hardware devices
Implement mechanisms for interacting with devices
Allocate and manage resources
Protection
Fairness
Obtain Efficient performance
Understand performance characteristics of device
Develop policies

3. I/O Subsystem User Process Kernel Kernel I/O Subsystem Software
Device
Drivers
SCSI
Bus
Keyboard
Mouse
PCI Bus
GPU
Harddisk
Software
Hardware
Device
Controllers
SCSI
Bus
Keyboard
Mouse
PCI Bus
GPU
Harddisk
SCSI
Bus
Keyboard
Mouse
PCI Bus
GPU
Harddisk
Devices

4. User View of I/O User Processes cannot have direct access to devices
Manage resources fairly
Protects data from access-control violations
Protect system from crashing
OS exports higher level functions
User process performs system calls (e.g. read() and write())
Blocking vs. Nonblocking I/O
Blocking: Suspends execution of process until I/O completes
Simple and easy to understand
Inefficient
Nonblocking: Returns from system calls immediately
Process is notified when I/O completes
Complex but better performance

5. User View: Types of devices
Character-stream
Transfer one byte (character) at a time
Interface: get() or put()
Implemented as restricted forms of read()/write()
Example: keyboard, mouse, modem, console
Block
Transfer blocks of bytes as a unit (defined by hardware)
Interface: read() and write()
Random access: seek() specifies which bytes to transfer next
Example: Disks and tapes

6. Kernel I/O Subsystem I/O scheduled from pool of requests Buffering
Requests rearranged to optimize efficiency
Example: Disk requests are reordered to reduce head seeks
Buffering
Deal with different transfer rates
Adjustable transfer sizes
Fragmentation and reassembly
Copy Semantics
Can calling process reuse buffer immediately?
Caching: Avoid device accesses as much as possible
I/O is SLOW
Block devices can read ahead

7. Device Drivers Encapsulate details of device
Wide variety of I/O devices (different manufacturers and features)
Kernel I/O subsystem not aware of hardware details
Load at boot time or on demand
IOCTLs: Special UNIX system call (I/O control)
Alternative to adding a new system call
Interface between user processes and device drivers
Device specific operation
Looks like a system call, but also takes a file descriptor argument
Why?

8. Device Driver: Device Configuration
Interactions directly with Device Controller
Special Instructions
Valid only in kernel mode
X86: In/Out instructions
No longer popular
Memory-mapped
Read and write operations in special memory regions
How are memory operations delivered to controller?
OS protects interfaces by not mapping memory into user processes
Some devices can map subsets of I/O space to processes
Buffer queues (i.e. network cards)

9. Interacting with Device Controllers
How to know when I/O is complete?
Polling
Disadvantage: Busy Waiting
CPU cycles wasted when I/O is slow
Often need to be careful with timing
Interrupts
Goal: Enable asynchronous events
Device signals CPU by asserting interrupt request line
CPU automatically jumps to Interrupt Service Routine
Interrupt vector: Table of ISR addresses
Indexed by interrupt number
Lower priority interrupts postponed until higher priority finished
Interrupts can nest
Disadvantage: Interrupts “interrupt” processing
Interrupt storms

10. Device Driver: Data transfer
Programmed I/O (PIO)
Initiate operation and read in every byte/word of data
Direct Memory Access (DMA)
Offload data xfer work to special-purpose processor
CPU configures DMA transfer
Writes DMA command block into main memory
Target addresses and xfer sizes
Give command block address to DMA engine
DMA engine xfers data from device to memory specified in command block
DMA engine raises interrupt when entire xfer is complete
Virtual or Physical address?

11. Interrupt Descriptor Table (IDT)
The IDT is a segment of memory containing pointers to irq handlers
For now think of them as function pointers
Location of the IDT configured using a special HW register (IDTR)
HW IRQ specifies which entry to use, called automatically by CPU

12. Interrupt Context

13. Exceptions Events generated by the CPU First 32 IRQ vectors in IDT
Page fault, Divide by zero, invalid instruction, etc
Full list in the CPU architecture manuals
First 32 IRQ vectors in IDT
Generally its an “error” or “exception” encountered during CPU instruction execution
IDT is referenced directly by the CPU
Completely internalized by HW

14. External Interrupts
Events triggered by devices connected to the system
Network packet arrivals, disk operation completion, timer updates, etc
Can be mapped to any IRQ vector above the exceptions
Vectors:
External because they happen outside the CPU
External logic signals CPU and notifies it which handler to execute
Managed by Interrupt Controller

15. Interrupt Controllers
Translate device IRQ signals to CPU IRQ vectors
Interrupt controller maps devices to vectors
Two x86 controller classes
Legacy: 8259 PIC
Connected to a set of default I/O ports on CPU
Modern: APIC + IOAPIC
Memory mapped into each CPUs physical memory

16. APIC How to support multiple CPUs SMP required a special solution
You only want one CPU to receive an interrupt
SMP required a special solution
APIC + IOAPIC
Separates the responsibility of the Interrupt Controller into two components
APIC = Interfaces with CPU
IOAPIC = Interfaces with devices

17. APIC Each CPU has its own local APIC
Tracks interrupts bound for its assigned CPU
Modern CPUs include APIC on the CPU die
APIC interfaces with CPUs interrupt pins to invoke correct IDT vector
But it does other things as well
Timer – APIC has its own embedded timer device
Allows each CPU to have its own timer
Inter-Processor Interrupt – Allows cross CPU communication
1 CPU can send an interrupt to another one

18. ICC bus APICs and IOAPICs share a common communication bus
ICC bus: Interrupt Controller Communication Bus
Handles routing of interrupts to the correct APIC

19. IOAPIC Connects devices to ICC bus
Translates device IRQ pins to CPU vectors
But now must also select destination APIC
Typically has 24 I/O Redirection Table Registers
Specifies vector # to send to APIC
Specifies which APIC (or group of APICS) can accept the IRQ
Several methods of specifying APIC addresses
Allows masking of IRQs from a device

20. Interrupt Vectors Vector Range Use 0-19
Nonmaskable interrupts and exceptions.
20-31
Intel-reserved
32-127
External interrupts (IRQs)
128
System Call exception
239
Local APIC timer interrupt
240
Local APIC thermal interrupt
Reserved by Linux for future use
Interprocessor interrupts
254
Local APIC error interrupt
255
Local APIC suprious interrupt

21. IRQ Example IRQ INT Hardware Device 32 Timer 1 33 Keyboard 2 3432
Timer 1 33
Keyboard 2 34
PIC Cascading 3 35
Second serial port 4 36
First serial port 6 38
Floppy Disk 8 40
System Clock 10 42
Network Interface 11 43
USB port, sound card 12 44
PS/2 Mouse 13 45
Math Coprocessor 14 46
EIDE first controller 15 47
EIDE second controller

22. Interrupt Handlers A function the kernel runs in response to interrupt
More than one handler can exist per IRQ
Must run quickly.
Resume execution of interrupted code.
How to deal with high work interrupts?

23. Top and Bottom Halves Top Half Bottom Half The “interrupt handler”
Disables lower priority interrupts
Runs in interrupt context, not process context.
Can’t sleep or block
Acknowledges receipt of interrupt.
Schedules bottom half to run later.
Re-enables Interrupts
Bottom Half
Runs in process context with interrupts enabled
Performs most work required
Can sleep or block
Eg. copies network data to memory buffers

24. Bottom Halves Three ways to defer work
SoftIRQs – Foundation for most bottom halves
Tasklets
Work Queues
ksoftirqd – Kernel thread to handle SoftIRQs
SoftIRQs may occur at high frequencies
Queues SoftIRQs and handles them in order
One thread per processor.
Runs at lowest priority (nice +19).

25. Timer Interrupt Executed HZ times a second.
#define HZ /* <asm/param.h> */
Called the tick rate.
Time between two interrupts is a tick.
Driven by Timer device
Several possible timer devices on modern HW
Interrupt handler responsibilities
Updating uptime, system time, kernel stats.
Rescheduling if current has exhausted time slice.
Balancing scheduler runqueues.
Running dynamic timers.