1. Instruction Packing for a 32-bit Stack-Based Processor Witcharat Lertteerawattana and Prabhas Chongstitvatana Department of Computer Engineering Chulalongkorn University

2. Motivation A stack-based processor (aka JVM) has many advantages
High-level instruction set
Simple and low cost data path
Code is compact
Disadvantage: limited performance

3. Motivation 2 In embedded systems, memory is a critical resource.
Stack-based instruction set is compact.
We propose instruction packing to compress the code segment.
The proposed processor is implemented based on FPGA devices.

4. Reference Processor

5. Instruction Type (Length)
Instruction Encoding
Entry Type
Instruction Type (Length) 00
No operation 01
Short Instruction 10
Medium Instruction 11
Long Instruction

6. Instruction Encoding 2
Added Entry-Type at front of each byte

7. Instruction Cycle

8. Decoding State (0)

9. Decoding State (1)

10. Modified Jump
Next-Byte opcode

11. Byte-Pointer Register

12. Packed Instruction

13. Performance

14. Comparing the number of cycles
Program
Ref. Processor
Packed Inst. Processor
Increased (%)
Bubble
59763
69061
15.58
Quick
21103
22373
6.02
Hanoi
52739
63040
19.52
Matmul
72260
91220
20.78

15. Comparing the code size (in byte)
Program
Ref. Processor
Packed Inst. Processor
Reduced (%)
Bubble
316
224
29.11
Quick
540
344
36.30
Hanoi
424
324
23.58
Matmul
784
556
29.08

16. Comparing the number of instruction fetch
Program
Ref. Processor
Packed Inst. Processor
Reduced (%)
Bubble
12549
8414
32.95
Quick
4542
3134
31.00
Hanoi
11005
8121
26.21
Matmul
15612
8563
45.15

17. Conclusion Code size reduced Amount of Instruction Fetch reduced
29.5%
Amount of Instruction Fetch reduced
33.8%
Speed also slightly reduced
15.4%