1. 0.13 m CMOS Technologies for Analog Front-end Circuits in LHC Detector Upgrades
M. Manghisoni, L. Ratti, V. Re, V. Speziali, G. Traversi
11th Workshop on Electronics for LHC
and future Experiments
12-16 September 2005, Heidelberg, Germany
Università di Pavia
Dipartimento di Elettronica
Università di Bergamo Dipartimento di Ingegneria Industriale
INFN
Sezione di Pavia

2. Outline Deep submicron CMOS technologies for detector readout
Investigated Technology: 0.13 µm CMOS process by STM
Experimental results from noise characterization
Channel thermal noise
1/f noise
Low noise preamplifier design criteria
Radiation hardness characterization
Conclusions
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

3. Deep submicron CMOS for detector readout
High functional density, low power, high speed, low noise  widely used for readout of high granularity detectors (microstrip, pixel)
High performance mixed signal systems were fabricated in 0.25 m CMOS processes
0.13 m processes for the new generation of strip and pixel detector readout systems (LHC upgrades, Linear Collider, Super B-Factory)
Thinning of the gate oxide associated to device scaling reduces the sensitivity to ionizing radiation
Design of preamplifier input device: behavior of noise parameters with gate length and width, drain current, oxide thickness
The impact of technology scaling on the analog and noise performances (white and 1/f noise at low current density) must be monitored
Data obtained from the measurements provide a powerful tool to model noise parameters and establish design criteria in a 0.13 m CMOS process for detector front-ends
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

4. Investigated Technology
Technology Features
0.13 m generation CMOS technology
STMicroelectronics HCMOS9 process
VDD = 1.2 V
oxide thickness: 2.4 nm
gate capacitance per unit area: COX=15 fF/ m2
Test Devices
Standard PMOS and NMOS devices
W = 200, 600, 1000 m
L = m
Standard open structure layout
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

5. Device operating region
In mixed-signal detector readout systems, power dissipation constraints set an upper limit on the drain current ID in the preamplifier input device
Devices were characterized at drain currents from 100 A to 1 mA
At such drain currents deep submicron devices are biased in weak or moderate inversion
A key parameter for the signal and noise performances of a CMOS device is the transconductance whose behavior depends on the operating region
Weak inversion 
VT=kT/q thermal voltage
n coefficient proportional to the inverse of the subthreshold slope of ID = f (VGS)
In weak inversion the transconductance is independent of gate geometry and device polarity
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

6. Noise in CMOS transistors
The noise performances of a MOS device can be characterized in terms of the gate-referred noise voltage spectrum
White noise:
Channel thermal noise (dominant at low current density)
Noise in parasitic resistors
1/f noise:
Kf = intrinsic process parameter
COX = OX/tOX (tOX=oxide thickness)
f = 1/f noise slope
The analysis of the experimental results includes the comparison of white and /f noise components of PMOS and NMOS devices with different geometries and characterized at different drain currents
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

7. Noise vs channel length and drain current
White Noise not sizably affected by L variations
1/f Noise increases when L decreases
White Noise decreases with the increase of ID due to the increase in transconductance
1/f Noise in NMOS not sizably affected by ID variations
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

8. Channel thermal Noise
The following relationship can be used in all inversion regions:
 ranges from 1/2 in weak inversion to 2/3 in strong inversion
n coefficient inversely proportional to the slope of the subthreshold region in the ID=f(VGS)
W = excess noise factor ( 1), may increase due to short channel effects
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

9. Channel Thermal Noise vs Drain Current
For both the polarity channel thermal noise decreases with the increase of the ID due to the increase of gm
White noise decreases for short channel devices except for the NMOS device with the minimum channel length allowed by the technology (L=0.13 m) which exhibits a larger thermal noise due to short channel effects
PMOS exhibits a slightly larger white noise due to the smaller transconductance
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

10. 1/f noise slope
The slope of the low frequency component of the spectrum differs from the case f=1
Values of f  1 were found for the PMOS, while f  1 for the NMOS
In the examined region, the parameter  f does not exhibit any clear dependence on the channel length L nor on the drain current ID
Typical values of the slope coefficient of the low frequency noise component are f = 1.2 for the PMOS and f = 0.85 for the NMOS
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

11. 1/f noise parameter Kf for NMOS
Coefficient Kf extracted from measurements on NMOS with L<0.35 mm is larger than for devices with longer channels
Avoid minimum channel length for NMOS devices implementing low-noise functions
In the examined region Kf does not exhibit any clear dependence on the drain current ID
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

12. 1/f noise parameter Kf for PMOS
A sizable increase of Kf both with the channel length L and the drain current ID is detected
In p-channel devices Kf increases with the overdrive voltage (VGS-VT)
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

13. Design of preamplifier input device
White and 1/f noise parameters extracted from measurements can be used to optimize the input device (gate dimensions, drain current) in detector applications
Equivalent Noise Charge in an analog processing channel
white noise
1/f noise
CT total capacitance at the preamplifier input, including the detector capacitance, the preamplifier input and feedback capacitance and strays
tP signal peaking time
A1 and A2 coefficients depending on the signal shaping
On the basis of this equation it is possible to estimate the noise limits of the 0.13 mm CMOS technology. The ENC is calculated assuming A1=1 and A2=0.5 which are close to the typical values for a good unipolar semigaussian shaper
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

14. Capacitive Matching
Equivalent Noise Charge as a function of the Ci/CD ratio (Ci is the preamplifier input capacitance, CD is the detector capacitance)
Minimum value attained for Ci/CD  0.15 for the NMOS and Ci/CD  0.2 for the PMOS  smaller than 1/3 (found for devices operating in strong inversion)
NMOS achieves a smaller ENC at a smaller Ci/CD since it operates closer to weak inversion with a larger transconductance gm
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

15. ENC and power consumption
Equivalent Noise Charge as a function of the power dissipation
At short processing times ENC can be reduced by increasing the power dissipation
If the power dissipation is increased, the optimum capacitive matching conditions are also changed, and the input capacitance Ci has to be adjusted by acting on the gate width
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

16. ENC and peaking time
Equivalent Noise Charge as a function of the peaking time
At peaking times beyond 80 ns the PMOS provides smaller ENC values
If peaking times exceeding 100 ns are compatible with the experimental constraints a PMOS-input preamplifier should be used to get better noise performances
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

17. Scaling impact on ENC ()
() Obtained from data presented by G. De Geronimo et al in "MOSFET Optimization in Deep Submicron Technology for Charge Amplifiers" (2004 IEEE NSS Conference Record)
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

18. 60Co -rays effects on device performances
Investigated devices were irradiated up to 10 MRad(SiO2) total dose with -rays 60Co source. The MOSFETs were biased during irradiation in the worst-case condition (PMOS: all terminals grounded, NMOS: 1.2 V on the gate relative to source, drain and body)
Characteristics unaffected for VGS  VT (very small threshold voltage shift)
Radiation-induced changes are apparent in the constant leakage current zone for both devices
increase in the subthreshold region in NMOS (edge effects due to radiation-induced charge at the STI oxide). Effect larger in devices with a shorter channel
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

19. 60Co -rays effects on noise
Channel thermal noise is affected to a very limited extent by ionizing radiation
Increase of 1/f noise is also very small for PMOS device and NMOS with a relatively long channel (L>0.5 mm)
In short-channel NMOS devices at low ID (around 100 mA) 1/f noise increases by a much larger extent than at higher drain currents
This may be correlated with the ID increase in the subthreshold region  STI oxide contributes in determining the 1/f noise properties of irradiated open-structure devices
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

20. Conclusions
This work presented a noise characterization of devices in a 0.13 mm CMOS technology
Parameters extracted from measurements are used to derive optimization criteria for the preamplifier input device in a detector analog readout channel
Technology exhibits a large degree of tolerance to ionizing radiation and it is suitable to the design of rad-hard analog circuits. Limitations concerning short- channel NMOS may arise at low drain current  low-noise NMOS should be implemented with an enclosed structure
Work is currently in progress to extend the experimental analysis to 0.13 mm devices from different foundries, with the goal of defining a more complete overview of the noise performances achievable with this CMOS generation
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

21. Backup slides 12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

22. 1/f noise energy parameter
If f = 1, Kf is a measure of 1/f noise “energy” in joules
If f ≠ 1, as it is often found in deep submicron devices, 1/f noise energy is dependent on frequency and can be defined by the parameter E1/f(f):
E1/f(f) at f = 10 kHz
The 1/f noise contribution appears to be larger in NMOS by about a factor of 10 for devices with the minimum channel length while a lower difference appears for longer channels
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments

23. Noise Measurement System
Low-noise transimpedance amplifier
gate/drain
bias circuit
Gain stage
Network/
Spectrum Anlyzer
DUT S
Bulk/Well
bias circuit
12-16 Sept 2005, Heidelberg
11th Workshop on Electronics for LHC and future Experiments