1. Chapter 4. Combinational Logic Design Principles

2. Logic circuits Combinational (조합) logic circuit
Outputs depend only on its current inputs
No feedback loop
Sequential (순차) logic circuit (chapters 7 & 8)
Outputs depend on its current inputs and present states
Feedback loop

3. Combinational logic circuits
A B A’
F = A’ + B
0 0
0 1
1 0
1 1 1
[Roth]

4. Sequential logic circuits 1 -
Inputs
not allowed
[S-R Latch]
[Roth]

5. Analysis, synthesis, and design
Analysis : logic diagram → truth table or logic expression
Synthesis : truth table or logic expression → logic diagram
Design
Truth table or logic expression (specification) → minimization →
gate selection → logic diagram → test

6. Analysis, synthesis, and design
[Roth]

7. Boolean algebra Boolean Algebra : 1854, George Boole,
Two valued (0 or 1) algebraic system
Analysis & design of digital circuits
Laws in Boolean Algebra
Commutative laws (교환법칙)
A + B = B + A , A • B = B • A
Associative laws (결합법칙)
A + ( B + C ) = ( A + B ) + C , A • ( B • C ) = ( A • B ) • C
Distributive laws (배분법칙)
A • ( B + C ) = A • B + A • C
Switching algebra [ 1938, C. Shannon : Bell lab. ]
Adapting Boolean Algebra to analyze & describe logic circuits
Relay logic ( open & close switch)

8. Switching algebra : operators & axioms
Algebraic Operators
NOT (complement) : prime ( ’ or )
AND (logical multiplication) : dot (•)
OR (logical addition) : plus (+)
Precedence (우선순위) : NOT > AND > OR
W•X+Y•Z = (W•X)+(Y•Z)
Axioms (공리)
[A1] X = 0 if X ≠ 1
[A2] if X = 0, then X’ = 1
[A3] 0 • 0 = [A3]’ = 1
[A4] 1 • 1 = 1 [A4]’ = 0
[A5] 0 • 1 = 1 • 0 = [A5]’ = = 1

9. Switching algebra theorems
▶ Switching algebra theorems with one variable
proof of (T3) X + X = X :
if X = 1, X + X = = 1 = X
X = 0, X + X = = 0 = X
using axioms

10. Switching algebra: two & three variables theorem

11. Switching algebra: two & three variables theorem
Commutative Laws:
Associative Laws:
Proof of Associate Law for AND
X Y Z
XY YZ
(XY)Z X(YZ)
[Roth]

12. Switching algebra: two & three variables theorem
AND OR
Distributive Laws:
Valid only switching algebra not for ordinary algebra
Proof of X+YZ=(X+Y)(X+Z) (using X(Y+Z)=XY+XZ)
[Roth]

13. Switching algebra: two & three variables theorem
Useful theorems for simplification
Proof
[Roth]

14. Switching algebra: two & three variables theorem
[Roth]
1. Combining terms
Example:
Adding terms using
Example:
2. Eliminating terms
Example:

15. Consensus theorem proof : [Roth] Consensus Theorem Example:
Dual form of consensus theorem
Example:

16. Switching algebra: two & three variables theorem
[Roth]
3. Eliminating literals
Example:
4. Adding redundant terms (Adding xx’, multiplying (x+x’), adding yz to xy+x’z, adding xy to x, etc…)
Example:
(add WZ’ by consensus theorem)
(eliminate WY’Z’)
(eliminate WZ’)

17. Simplification of logic circuits
Equivalent gate circuits
===
[Roth]

18. Switching algebra: n-variables theorems

19. De Morgan’s theorem [Roth] DeMorgan’s Laws Proof
X Y
X’ Y’
X + Y
( X + Y )’ XY
( XY )’
X’ + Y’
0 0
0 1
1 0
1 1 1
DeMorgan’s Laws for n variables
Example

20. De Morgan’s theorem ⅰ) AND-Invert ≡ Invert-OR ex) (X • Y) = X + Y
ⅱ) OR-Invert ≡ Invert-AND
ex) (X + Y) = X • Y

21. Generalized De Morgan’s theorem
[F ( X1, X2, • • • Xn, + , • )]’ = F (X1’, X2’, • • • Xn’, • , + )
ex) F ( A, B, C, D ) = D’ • A + A • B + D • ( A’ + C’ )
[F (A, B, C, D)]’ = [D’A + AB + D(A’+C’)]’
= (D’A)’ • (AB )’ • (D(A’+ C’))’
= ( D + A’ )( A’ + B’ )( D’ + AC )
ex) F = (AB)’C + A(B+C’)
F’ = ((AB)’C)’ • (A(B+C’))’
= (AB+C’) (A’+(B+C’)’)
= (AB+C’) (A’+B’C)

22. Duality Dual of a logic expression F(X1,X2,…, Xn,+,•)
FD(X1,X2,…, Xn,+, •) = F(X1,X2,…, Xn,•,+)
Principle of Duality
Any theorem or identity in switching algebra remains true if 0 and 1 are swapped and • and + are swapped throughout
Ex.) (T10) X • Y + X • Y´ = X
Dual of (T10) → (X + Y) • (X + Y´) = X → True??
→ Yes, it is true because it is (T10)´
It doubles the usefulness of everything that you learn about switching algebra and manipulation of switching functions

23. Source of duality : positive & negative logics
Positive Logic
HIGH = 1 & LOW = 0
Negative Logic
HIGH = 0 & LOW = 1
[ positive logic]
[ negative logic]

24. Source of duality : positive & negative logics
[ positive logic]
[ negative logic]
Given a logic expression F(X1,X2,…, Xn,+,•)
→ [F(X1,X2,…, Xn,+,•)]´ = FD(X1´,X2´,…, Xn´,+,•)
→ [F(X1,X2,…, Xn,+,•)]´ = F(X1´,X2´,…, Xn´,•,+)
→ DeMorgan’s Theorem !!!

25. Duality

26. Standard representation of logic functions
- basic representation method → truth table
ex) n-variable logic function → 2n rows in truth table
ex) 3 variable logic function : F( X, Y, Z ) => table 4- 4 , 5
- basic representation method → algebraic expressions
ex) F = X´Y´Z´ + X´YZ + XY´Z´ → Sum of products expression
ex) F = (X+Y+Z´)(X+Y´+Z)(X´+Y+Z´) → Product of sums expression

27. Standard representation of logic functions
Sum of product form:
Product of sum form:
[Roth]

28. Canonical sum & product representations
Canonical sum of a logic function F(X,Y,Z)
A sum of the minterms corresponding to truth-table rows for which the function produces a 1 output
Canonical product of a logic function F(X,Y,Z)
A product of the maxterms corresponding to truth-table rows for which the function produces a 0 output

29. Canonical sum & product representations
Canonical sum of F
F = ∑X,Y,Z(0,3,4,6,7)
= X´Y´Z´ + X´YZ + XY´Z´ + XYZ´ + XYZ
Canonical product of F
F = ∏X,Y,Z(1,2,5)
= (X+Y+Z´)(X+Y´+Z)(X´+Y+Z´)
F = ∑X,Y,Z(0,3,4,6,7) = ∏X,Y,Z(1,2,5)

30. Levels of gates in logic circuits
The maximum number of gates cascaded in series between a circuit input and the output
Usually, all variables and their complements are available as circuit inputs
Four-Level Realization of Z
[Roth]

31. Combinational circuit analysis
ⅰ) Exhaustive approach : truth table
Fig 4-10 Gate outputs created by all input combination
ⅱ) Algebraic approach : fig 4-11,12,13 • • • •

32. Combinational circuit analysis
‣ f = ( X + Y ) Z + X • Y • Z
= X Z + Y Z + X Y Z => Fig 4-12 (2-level AND-OR circuit)
= ( X • Y • Z + X + Y ) ( X • Y • Z + Z )
= ( X + Y + Z ) ( X • Y + Z )
= ( X + Y + Z ) ( X + Z ) ( Y + Z ) => Fig 4-13 (2-level OR-AND) • • • • B C A
A+B•C = (A+B)(A+C)
by distribution laws
[Fig. 4-12]
[Fig. 4-13]

33. Combinational circuit analysis
When we simplify a logic expression using the theorems of switching algebra, we get an expression corresponding to a different circuit
F = [ (( W • X ) • Y ) + ( W + X + Y ) + ( W + Z ) ]

34. Combinational circuit analysis
F = [ (( W • X ) • Y ) + ( W + X + Y ) + ( W + Z ) ]
= (( W + X ) + Y ) • ( W • X • Y ) • ( W • Z )
= (( W • X ) • Y ) • ( W + X + Y ) • ( W + Z )
= (( W + X ) • Y ) • ( W + X + Y ) • ( W + Z )
: by De Morgan’s theorem

35. Combinational circuit synthesis
A starting point for designing logic circuits
Usually, we are given a word description of a problem
For example, “Design 4-bit prime number detector”
We can express the word description as a algebraic logic expression or truth table by hand
Circuit minimization
In modern digital-design environments, we can translate the word description into a HDL program
Designers never gets involved in synthesis at all

36. Combinational circuit synthesis
Circuit description & design :
ex-1) 4-bit prime number detection
f = ∑ ( 1,2,3,5,7,11,13 )
f = ∑ ( 1,2,3,5,7,11,13 )
= N3N2N1N0 + N3N2N1N0 + N3N2N1N0 + N3N2N1N0 + N3N2N1N0
+ N3N2N1N0 + N3N2N1N0
N3N2N1N0
Canonical sum of product design

37. Combinational circuit synthesis
ex-2) Alarm circuit design:
“The ALARM output is 1 if the PANIC input is 1, or if the ENABLE
input is 1, the EXITING input is 0, and the house is not secure;
the house is secure if the WINDOW, DOOR, and GARAGE inputs are
all 1.”
ALARM = PANIC + ENABLE • EXITING • SECURE
SECURE = WINDOW • DOOR • GARAGE
=> Fig 4-19, 20
Fig Alarm circuit derived from logic expression

38. Circuit manipulations
- NAND & NOR : i) less # of transistors than AND & OR
ii) faster than AND & OR
ex-1 NAND-NAND
Fig 4-21 Alternative sum of products realizations
a) AND-OR b) AND-OR with extra inverter pairs
c) NAND-NAND

39. Circuit manipulations
Any sum-of-products expression can be realized in two ways
AND-OR circuit
NAND-NAND circuit
Any product-of-sums expression can be realized in two ways
OR-AND circuit
NOR-NOR circuit

40. Circuit manipulations
ex-3 Fig 4-24
Nonstandard gate

41. 8 basic forms for two-level circuits
[Roth]

42. Combinational-circuit minimization
Canonical forms are expensive
The number of possible minterms or maxterms grows exponentially with the number of input variables.
The minimization methods for 2-level circuits
Minimizing the number of first-level gates
Minimizing the number of inputs on each first-level gates

43. Combinational-circuit minimization
Cost of input inverters -> do not consider
-> appropriate for PLD-based design
- most minimization method : T10 & T10 (Combining theorems)
XYZ + XYZ = XY : minterm
( X+Y+Z )( X+Y+Z ) = X+Y : maxterm
(given product term • Y ) + ( given product term • Y ) = given product term
(given sum term + Y ) • ( given sum term + Y ) = given sum term
Simplification method
ⅰ) Boolean Algebra : De-Morgan, Shannon Expansion, •••
ⅱ) Map method : • Karnaugh method
• McCluskey method ( Tabular method )
• Consensus method

44. Combinational-circuit minimization
- Simplified sum of product realization for 4-bit prime number detector
N3N2N1N0
f = ∑ ( 1,3,5,7,2,11,13 )
= N3N2N1N0 + N3N2N1N0 + N3N2N1N0 + N3N2N1N0 + …
= ( N3N2N1N0 + N3N2N1N0 ) + (N3N2N1N0 + N3N2N1N0 ) + …
= N3N2N0 + N3N2N0 + …
= N3N0 + …
Most minimization methods are
based on the combining theorem • • • • • • • • • •

45. Karnaugh maps ▶ Karnaugh maps method
Karnaugh map : modification of the Veitch diagram
- variable map : Fig 4-26
‣ adjust square ( = gray code )
Venn diagram
WXYZ = 1110 = 14
XYZ = 101 = 5

46. F(A,B) = ∑( 0,1 ) = A´B´ + A´B = A´
Karnaugh maps
F(A,B) = ∑( 0,1 ) = A´B´ + A´B = A´
A B F
0 0
0 1
1 0
1 1 1
(a)
1-cell
[Roth]

47. Karnaugh maps
[Roth]

48. Karnaugh maps
[Roth]

49. Karnaugh maps z ex-1) f ( X,Y,Z ) = ∑ ( 0,1,4,5,6 )
rectangular set of 22 1s
rectangular set of 21 1s z
XZ´Y + XZ´Y´ = XZ´

50. Karnaugh maps
Function with Two Minimal Forms
[Roth]

51. Consensus term is redundant
Karnaugh maps
Karnaugh Maps Which Illustrate the Consensus Theorem
Consensus term is redundant
[Roth]

52. Karnaugh maps
[Roth]

53. Karnaugh maps
[Roth]

54. Karnaugh maps ex-2) Prime NO. detector : Fig 4-30
Fig 4-30 Prime-number detector

55. Karnaugh maps A minimal sum of a logic function F(X1,…,Xn)
A sum-of-products expression for F such that no sum-of-products expression for F has fewer product terms, and any sum-of-products expression with the same number of product terms has at least as many literals
4 product terms
14 first-level gate inputs
4 product terms
11 first-level gate inputs
→ minimal sum

56. Karnaugh maps A prime implicant of a logic function F(X1,…,Xn)
A product term is called a prime implicant if it cannot be combined with another term to eliminate a variable
Prime Implicant Theorem
A minimal sum is a sum of prime implicants
ex-3) F = ∑ ( 5,7,12,13,14,15 ) : fig 4-31
2 prime implicants

57. Karnaugh maps A distinguished 1-cell of a logic function
ex-4) F = ∑ ( 1,3,4,5,9,11,12,13,14,15 ) : fig 4-33
‣ 5 prime implicants
‣ 3 essential prime implicants
(thick circles)
‣ 3 distinguished 1-cells
(shaded cells)
A distinguished 1-cell of a logic function
An input combination that is covered by only one prime implicant
An essential prime implicant of a logic function
A prime implicant that covers one or more distinguished 1-cells
It must be included in every minimal sum for the logic function

58. Karnaugh maps
ex-5) F = ∑ ( 2,3,4,5,6,7,11,13,15 ) : fig 4-33
All of the prime implicants are essential, and so all are included in the minimal sum

59. Karnaugh maps
When a logic function in which not all the 1-cells are covered by
essential prime implicants
ex-6) F = ∑ ( 0,1,2,3,4,5,7,14,15 ) : fig 4-34
E.P.I
Distinguished
1-Cell
F = E.P.I + W Z = W Y + W X + W X Y + W Z

60. Karnaugh maps essential prime implicants ex-7) Secondary E.P.I
F = ∑ ( 2,6,7,9,13,15 ) : fig 4-35
essential prime implicants

61. Karnaugh maps A logic function with no essential prime implicants
By trial and error method
Branching method
ex-8) Several different minimal sums
F = ∑ (1,5,7,9,11,15 ) : fig 4-36 z
2 minimal sums

62. Simplifying products of sums
The way to find to a minimal product of a logic function F
Complement F to obtain F´
The 1s of F´ are just the 0s of F
Find a minimal sum for F´
Complement the result using the DeMorgan’s theorem
ex) F = ∑ ( 2,3,4,5,6,7,11,13,15 )
F´ = X´Y´ + WZ´
DeMorgan’s The.
F = (X+Y)(W´+Z)

63. Simplifying products of sums
ex) F = ∑ ( 2,3,4,5,6,7,11,13,15 )
F´ = X´Y´ + WZ´
DeMorgan’s The.
F = (X+Y)(W´+Z)
More lower-cost than
the minimal sum
A minimal sum may not be a lowest-cost realization, and vice versa
In general, to find the lowest-cost two-level realization of a logic function, we have to find both a minimal sum and a minimal product and compare them

64. Don’t-care input ▶ Don’t care input combinations = =
- Don’t care : output doesn’t matter for certain input combinations
ex-1) prime number detection for BCD , 10 ~ 15 : should never occur
f = ∑ ( 1,2,3,5,7 ) + d ( 10,11,12,13,14,15 ) = =
Prime BCD detection
Don’t care term

65. Multiple-output minimization
- Two output functions
F = ∑ ( 3,6,7 ) = XY + YZ
G = ∑ ( 0,1,3 ) = X´Y´ + X´Z
ⅰ) Two independent single output design

66. Multiple-output minimization
Shared term
f = X Y + X´Y Z
g = X´Y´ + X´Y Z
Same input combination = shared term
If we use PLDs , product terms can be shared among
multiple output

67. Five & six variables maps
▶ five & six variable map ⅰ)
Gray code •• ⅱ) CD CD AB AB
E = 0
E = 1
ex ) f = ∑ ( 0,2,4,6,9,11,13,15,17,21,25,27,29,31 )
= B E + A B E + A B E
F = 0
F = 1 ⅲ) ⅳ) DE DE AB AB
C = 0
•••
C = 1 ••
Gray code
Anding product function

68. Five & six variables maps
ex ) f = ∑ ( 2,5,7,8,10,13,15,17,19,21,23,24,29,31 )
= CE + AB’E + A’C’DE’ + BC’D’E’
A=0
A=1 BC DE BC DE 00 01 11 10 00 01 11 10 00 1 00 1 01 1 1 01 1 1 1 11 1 1
BC’D’E’ 11 1 1 1 10 1 1 10
AB’E
A’C’DE’ CE

69. Design of circuits with limited gate fan-in
Example: Realize using 3-input NOR gate
[Roth]

70. Design of circuits with limited gate fan-in
f’ = b’d(a’c’+ac)+a’c(b+d’)+abc’
f = [b+d’+(a+c)(a’+c’)][a+c’+b’d][a’+b’+c]
[Roth]

71. Programmed minimization methods
■ Tabular method
Quine & Mccluskey method
‣ use for functions with fewer than 15~20 variables
ⅰ) finding all prime implicant
ⅱ) selecting a minimal set of prime implicant
- procedure
ⅰ) arrange all minterms in group with ‘1’
ⅱ) combine every term of successive group using “ AB + AB = A ”
Choice table ( or called prime-implicant tables)

72. Quine-McCluskey algorithms
ex-1) f = ∑ ( 0,1,2,8,10,11,14,15 )
- 1st reduction
- term arrange
- 2st reduction
Prime implicant
- choice table
1 cells
prime implicant minterm
distinguished 1-cells
F = A´B´C´ + B´D´ + AC

73. Quine-McCluskey algorithms
ex-2) f = ∑ ( 0,4,5,6,11,12,13,14,15 )
ⅰ) term arrange
1st reduction
2st reduction
ⅱ) Selection of prime implicants (choice table)
1 cell
Prime
implicant
f = ACD + ACD + BC + BD

74. Quine-McCluskey algorithms
ex-3) f = ∑ ( 3,5,7,8,10,11,12,13,15 ) + d ( 0,2 )
ⅰ) term arrange
1st reduction
2st reduction

75. Quine-McCluskey algorithms
ⅱ) Selection of prime implicants (choice table)
ⅱ) 2st choice table
f = BD + BC + ACD

76. Timing hazards [Roth] Propagation Delay in an Inverter
Timing Diagram for AND-NOR Circuit

77. Timing hazards Timing hazards ▶ Static hazards - steady state behavior
ignore gate delay
however circuit delay → exist in real circuits,
transient behavior = glitch ( short pulse )
▶ Static hazards
ⅰ) static 1-hazards : only one input → differ
both give 1-output
momentary 0-output
ex) AND-OR circuits with static-1 hazard 1
1 → 0 1

78. Problems caused by timing hazards
The value of a glitch signal may be used without waiting for it to settle to its final value
Can be solved by controlling a system’s clock period
The value of a signal may be connected to asynchronous inputs
More difficult problem

79. Timing hazards ⅱ) Static 0-hazard : differ only one input
both give 0-output
momentary 1-output
ex) OR-AND circuits with static-0 hazard
Not properly designed AND gate : static-0 hazard 
- Not properly designed OR gate : static-1 hazard 

80. Detection and prevention of static hazards using Karanugh maps
ex-1) hazard free circuits
a) it may create static-1 hazard
b) eliminate hazard by including
extra product term =
‘consensus’ of two term
XZ´ + YZ + XY =
Hazard free circuit
Circuit with static-1 hazard eliminated

81. Detection and prevention of static hazards using Karanugh maps
ex-2)
Hazard
free circuit
Fig 4-48 Karnaugh map for another sum-of products circuit
extra product term to connect 3 prime implicants
( by consensus theorem )
XY´Z´ + W´Z = W´XY´
W´Z + WY = YZ
XY´Z´ + WY = WXZ´

82. Detection and prevention of static hazards using Karanugh maps
Detection of a static 0-Hazard 1
Inverter delay = 3ns
AND, OR gates delay = 5ns
[Roth]

83. Detection and prevention of static hazards using Karanugh maps
[Roth]
Karnaugh Map Removing Hazards

84. Dynamic hazards ▶ Dynamic hazards
- output → change more than once as single input transition
multiple path different gate delay form input to output
Assumption :all of the gates except “slow” and “slower” gates are very fast

85. Hazard-free assumption
Hazard-free techniques assume that only single-bit change in the inputs may result in the unexpected changes in the outputs.
The techniques simply do not apply when more than one input bit changes at the same time.
Hazards caused by simultaneous multiple-input changes are unavoidable

86. Dynamic hazards
Dynamic hazards do not occur in a properly designed two-level AND-OR or OR-AND circuit
No variable and its complement are connected to the same first-level gate
In multilevel circuits, dynamic hazards can be discovered using various methods
Properly designed AND-OR circuits
No static-0 hazard and dynamic hazard
Applied to NAND-NAND designs
Properly designed OR-AND circuits
No static-1 hazard and dynamic hazard
Applied to NOR-NOR designs