Download presentation
Presentation is loading. Please wait.
1
CDA3101 Recitation Section 8
MIPS Pipeline and Hazards
2
MIPS Single Cycle Data Path
Problem: all instructions take the same length of time, only one piece of hardware in use at any time Clock rate determined by critical path.
3
Motivation for Multicycle Data Path
Design a minimal piece of hardware that can handle every step of the path, but only one at a time. Each instruction passes through this hardware multiple times. Clock rate determined by slowest functional unit. Advantage: less wasted hardware – each unit can be re-used by an instruction Advantage: not all instructions take same number of cycles
4
MIPS Multi Cycle Data Path
5
Motivation for Pipelining
Goal is to have every block of hardware working as much as possible. Multi-cycle approach involves complex control unit, and jack-of-all-trades hardware. An “assembly-line” approach is more efficient. Solution: break instruction execution into stages, then “pipe” the output of each stage into the next stage. Clock rate determined by slowest stage.
6
Pipeline Stages MIPS Pipeline Stages IF – Instruction Fetch
ID – Instruction Decode / Data Fetch EX – Execute MEM – Memory Access WB – Writeback to registers Buffers at the start of each stage.
7
Pipeline Stages
8
Pipeline Stages
9
Pipeline Stages Instructions passing through the pipeline
10
What could go wrong? (Hazards)
Data Hazard: an instruction depends on a result computed by a previous instruction that is not ready Control Hazard: the result of a branch is not known until after subsequent instructions enter the pipeline Structural Hazards: different instructions try to access the same piece of hardware
11
Dealing with Structural Hazards
Structural Hazards: different instructions try to access the same piece of hardware Solutions: Duplicating Hardware: example – branch instruction requires a compare and subtract in same clock cycle, so we have two add units. Hardware Concurrency: example - register file writes at first half of the clock cycle, and reads on second half to support ID and WB; memory also supports two reads for IF and MEM Reordering: instructions can be reordered to eliminate conflicts (examples coming later)
12
Data Hazards Data Hazard: an instruction depends on a result computed by a previous instruction that is not ready RAR - read after read WAR - write after read WAW - write after write RAW - read after write (problem)
13
Dealing with Data Hazards
Solutions Stall Insertion: send dummy instructions (stalls) into the pipeline Code Reordering: send an instruction from another dependency chain into the pipeline Forwarding: add hardware to send the dependency information to the instruction that needs it
14
Problem 1: Data Hazards Resolve the data hazards in the MIPS code above using (i) stalls, (ii) code-reordering (iii) forwarding add $1 $2 $3 add $4 $1 $1 add $11 $12 $13 Add $14 $11 $11 *Note: do not assume the existence of a register file that can read/write at half clock cycles
15
Problem 1: Data Hazards $1 needed $1 ready $11 needed $11 ready CC1
add $1 $2 $3 add $4 $1 $1 add $11 $12 $13 add $14 $11 $11 IF ID ALU MEM WB IF ID ALU MEM WB IF ID ALU MEM WB IF ID ALU MEM WB $11 needed $11 ready CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 CCA CCB CCC CCD
16
Problem 1: Data Hazards i. stalls CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9
CCA CCB CCC CCD add $1 $2 $3 stall add $4 $1 $1 add $11 $12 $13 add $14 $11 $11 IF ID ALU MEM WB IF ID ALU MEM WB IF ID ALU MEM WB IF ID ALU MEM WB
17
Problem 1: Data Hazards ii. reordering CC1 CC2 CC3 CC4 CC5 CC6 CC7 CC8
CCA CCB CCC CCD add $1 $2 $3 add $11 $12 $13 stall add $4 $1 $1 add $14 $11 $11 IF ID ALU MEM WB IF ID ALU MEM WB IF ID ALU MEM WB IF ID ALU MEM WB
18
Problem 1: Data Hazards iii. forwarding CC1 CC2 CC3 CC4 CC5 CC6 CC7
CCA CCB CCC CCD add $1 $2 $3 add $4 $1 $1 add $11 $12 $13 add $14 $11 $11 IF ID ALU MEM WB IF ID ALU MEM WB IF ID ALU MEM WB IF ID ALU MEM WB
Similar presentations
![1 ECE369 ECE369 Pipelining. 2 ECE369 addm (rs), rt # Memory[R[rs]] = R[rt] + Memory[R[rs]]; Assume that we can read and write the memory in the same cycle.](/11/3333572/big_thumb.jpg "1 ECE369 ECE369 Pipelining. 2 ECE369 addm (rs), rt # Memory[R[rs]] = R[rt] + Memory[R[rs]]; Assume that we can read and write the memory in the same cycle.>")
