1. Floating gate memory based on MoS2 channel and iCVD polymer dielectric
with metal nanoparticle charge trapping layer
The 3rd Korean Graphene Symposium
PB-20
Myung Hun Woo1, Byung Chul Jang1, Junhwan Choi2, Gwang Hyuk Shin1, Hyejeong Seong2, Sung Gap Im2, Sung-Yool Choi1
1 School of Electrical Engineering and Graphene Research Center, KAIST
2 Department of Chemical and Biomolecular Engineering & KI for NanoCentury, KAIST
Research on the layered two-dimensional (2D) materials has significantly increased in electronics, photonics, energy application and flexible device application due to its unique properties such as sub-1nm thickness, layer dependent band gap and high intrinsic mobility. One promising application of 2D materials is nonvolatile memory which is regarded as a core industry for the present and future in the semiconductor field. In this work, we fabricated the floating gate memory based on MoS2 with polymer tunneling dielectric layer. Here, initiated chemical vapor deposition (iCVD) process was used to deposit tunneling dielectric. Subsequently, effectively tunable gold nanoparticle structure via thermal evaporation method was used as a charge trapping layer with Al2O3 blocking oxide which is deposited by ALD process to increase the gate coupling ratio for high performance of the memory device. The fabricated device showed a stable memory characteristics and a large tunable threshold voltage (VT) shift in accordance with the pulse width and DC bias sweep variation of control gate, which allows the multi-bit data storage. The polymer tunneling dielectrics based on iCVD process is expected to play a key role in the future development of a nonvolatile memory device based on 2D materials as a substitute for ALD dielectrics.
I. Introduction
II. Device fabrication
1. MoS2 (Molybdenum disulfide)
1. Floating gate memory device fabrication process
MoS2
 One of promising two dimensional material
 Atomically thin structure, high mobility, flexibility, high transparency
2-D material, MoS2
Bandgap
direct bandgap 1.8eV (single-layer)
Thermal stability
> 1090 [oC ]
Young’s modulus
270 [Gpa]
Mobility
1~150 [cm2/V∙s] (layer dependence)
On/off current ratio
107~108
Subthreshold Swing
60~80 [mV/dec.] (layer dependence)
Velocity saturation
0.3 x 107 [cm/s] (silicon: 1.02 x 107)
Critical E-field
2 x 106 [V/cm] (silicon: 4 x 104)
Hysteresis
ΔVth < 0.01 V (hBN Encap.) sweep range: -20 ~120 V
III. Results & Analysis
The first figure, which is the back gate device electrical properties based on the mechanically exfoliated MoS2, shows clear switching operation with high on/off ratio(~108) and high field effect mobility(~18.6cm2/Vs) of the device. As a control device, dual gate dielectric device without Au nanoparticle layer shows almost no hysteresis under DC bias sweeping in second figure. It means that the device has no memory characteristics. The last figure exhibits clear ohmic-like contact of the fabricated device.
2. Floating gate memory
Device structure and it’s mechanism
 Memory states are decided based on the amount of the trapped charge in the charge storage layer, which is depend on the bias or pulse condition of control gate (CG).
Enze Zhang, et al. ACS Nano (2015)
3. Motivation
The DC bias sweep started from -12V of the fabricated memory device shows clear hysteresis of the transfer characteristics in the first figure. In the second figure, the stable memory states with high Ion/off ratio on Vg=0V for ~103s after ±13V control gate pulse for 3s was observable. With the tunable memory window based on the variation of the pulse width, all datas illustrate that the device clearly operates as a memory.
The absence of dangling bonds on 2D materials
 The adsorption of ALD precursors on 2D materials is so weak due to the lack of dangling bonds on the surface.
 Pulse action pushes The precursor molecules are pushed to the lowest potential energy by pulse action and pushed away from substrate on purge time.
 By using initiated chemical vapor deposition (iCVD), ultra-thin polymer dielectric layer under low temperature is possible to substitute the ALD-based dielectric layer with approving the applicability of polymer dielectric with 2D materials.
4. pV3D3 properties
pV3D3
 initiated CVD method : adsorbed monomers onto the surface are polymerized via reacting with initiator radicals.
 Conformal coverage, solvent free, no surface or substrate limitations.
IV. Conclusion
iCVD process
In this work, we fabricated the floating gate memory based on MoS2 channel and pV3D3 iCVD polymer dielectric with Au nanoparticle charge trapping layer. At first, the electrical properties of the dual dielectric top gate device without charge trapping layer shows the possibility of pV3D3 polymer layer as a tunneling dielectric layer of memory device. Following transfer characteristics with memory window variation based on the control gate pulse width show tunable charge trapping density of the device. The stable program/erase state for 103s also exhibits the memory property. This data will contribute to further research on memory based on MoS2.
M, I flow
Heated filaments
Initiator
decomposition
Adsorption
Surface polymerization I M R + P
Acknowledgement
This work was supported by the Global Frontier Center for Advanced Soft Electronics ( ), the Creative Research Program of the ETRI (13ZE1110), and KI Research Project.
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Reference
Simone Bertolazzi et al., ACS Nano. 7(4), p.3246 (2013)
Enze Zhang et al., ACS Nano. 9(1), p.612 (2015)
Hanul Moon et al., Nat. Materials, (2015)