1. Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Chapter 7
Transfer Gate and Dynamic Logic Design
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.

2. 7.2 Basic concepts

3. 7.2.1 Pass Transistors

4. 7.2.1 Pass Transistors

5. 7.2.1 Pass Transistors

6. 7.2.2 Capacitive Feedthrough

7. 7.2.2 Capacitive Feedthrough

8. 7.2.2 Capacitive Feedthrough
from charge equations
(7.1)
(7.2)
(7.3)

9. 7.2.3 Charge Sharing

10. (7.4) (7.5) (7.6) 7.2.3 Charge Sharing from total charge equations
Final voltage after charge exchange
(7.4)
(7.5)
(7.6)

11. 7.3 CMOS Transmission gate logic

12. Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
7.3 CMOS Transmission Gate Logic
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.

13. 7.3 CMOS Transmission Gate Logic

14. 7.3.1 Multiplexers Using CMOS Transfer Gates

15. 7.3.1 Multiplexers Using CMOS Transfer Gates

16. 7.3.1 Multiplexers Using CMOS Transfer Gates

17. 7.3.1 Multiplexers Using CMOS Transfer Gates

18. 7.3.1 Multiplexers Using CMOS Transfer Gates

19. 7.3.1 Multiplexers Using CMOS Transfer Gates

20. 7.3.2 CMOS Transmission Gate Delays

21. 7.3.2 CMOS Transmission Gate Delays
Large-signal resistance (Figure 7.8)
NMOS
saturation
linear
PMOS

22. 7.3.2 CMOS Transmission Gate Delays
Large-signal resistance (Figure 7.8)
PMOS
saturation
linear
NMOS

23. 7.3.2 CMOS Transmission Gate Delays

24. 7.3.2 CMOS Transmission Gate Delays
On-resistance
All resistance
(7.7)

25. 7.3.2 CMOS Transmission Gate Delays

26. (7.8) (7.9) (7.10) (7.11) 7.3.2 CMOS Transmission Gate Delays
Input and output capacitances
(7.8)
(7.9)
(7.10)
(7.11)

27. 7.3.2 CMOS Transmission Gate Delays

28. 7.3.2 CMOS Transmission Gate Delays
Elmore delay equation

29. 7.3.3 Logical Effort with CMOS Transmission Gates

30. 7.3.3 Logical Effort with CMOS Transmission Gates

31. 7.4 dynamic d-latches and d flip-flops

32. 7.4 Dynamic D-Latches and D Flip-Flops

33. 7.4 Dynamic D-Latches and D Flip-Flops

34. 7.4 Dynamic D-Latches and D Flip-Flops

35. 7.4 Dynamic D-Latches and D Flip-Flops

36. 7.5 Domino logic

37. 7.5 Domino Logic

38. 7.5 Domino Logic

39. 7.5 Domino Logic

40. 7.5 Domino Logic

41. 7.5.1 Logical Effort for Domino Gates

42. 7.5.1 Logical Effort for Domino Gates
LE values
for inverter size of 8 for the pull-up and 4 for the pull down
for the domino circuit (simply 8 )

43. Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
7.5.2 Limitations of Domino Logic
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.

44. 7.5.2 Limitations of Domino Logic
Final voltage after charge exchange

45. 7.5.2 Limitations of Domino Logic

46. 7.5.3 Dual-Rail (Differential) Domino Logic

47. 7.5.3 Dual-Rail (Differential) Domino Logic

48. 7.5.3 Dual-Rail (Differential) Domino Logic

49. 7.5.4 Self-Resetting Circuits

50. 7.6 summary

51. 7.6 Summary
Capacitive feedthrough and bootstrapping equation
Charge-sharing equation
Large-signal resistance for CMOS transmission gate