1. Pass-Transistor Logic

2. Pass-Transistor Logic
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Pass-Transistor Logic
Allow inputs to drive source/drain terminals as well as gate terminals

3. EE141
Example: AND Gate
Is B redundant?

4. EE141
NMOS-Only Logic
Unfortunately, NMOS passes strong 0 but weak 1 (the situation is even worsened by body effect)
0.5 1
1.5 2
0.0
1.0
2.0
3.0
Time [ns] V o l t a g e
[V] x
Out In
Avoid cascading multiple pass-logic (without buffering)!!!

5. NMOS-only Switch V V does not pull up to 2.5V, but 2.5V -
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NMOS-only Switch
A =
2.5 V B
C =
2.5 V C L M 2 1 n V
does not pull up to 2.5V, but 2.5V - V B TN
Though smaller voltage swing causes smaller dynamic
power consumption, threshold voltage loss causes
static power consumption of following inverters

6. Differential Pass Transistor Logic (DPTL)
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Differential Pass Transistor Logic (DPTL)

7. EE141
Properties of DPTL
Similar to DCVSL, it accepts true and complementary inputs and produce true and complementary outputs
Some complex gates such XORs and adders can be realized efficiently with a small number of transistors. It also eliminates the need for extra inverters (delay symmetric).
DPTL is static, because the output defining nodes are always connected to either VDD or GND via low-resistance path (good for noise)
Design is very modular, which makes designing a library of gates simple. More complex gates can be built by cascading the modules.
Some routing overhead due to complementary input/output

8. Robust Pass transistor logic: solution 1 Level Restoring Transistor
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Robust Pass transistor logic: solution 1 Level Restoring Transistor V DD V
Level Restorer DD M r B M 2 X A M n
Out M 1
• Advantage: Full Swing and no static power consumption
• Restorer adds capacitance, positive on L-H delay but negative on H-L
• Ratio problem when output transitions from H-to-L
Mr size large or small?
Small for large resistance

9. EE141
Restorer Sizing
100
200
300
400
500
0.0
1.0
2.0 W / L r
=1.0/0.25
=1.25/0.25
=1.50/0.25
=1.75/0.25 V o l t a g e
[V]
Time [ps]
3.0

10. Solution 2: NMOS Pass Gate with VT=0
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Solution 2: NMOS Pass Gate with VT=0
Out V DD
2.5V 0V
Zero VTN NMOS
Source-body effect might still prevent full swing
WATCH OUT FOR LEAKAGE CURRENTS!!!

11. Solution 3: Transmission Gate
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Solution 3: Transmission Gate C C A B A B C C
C =
2.5 V
Can reach 2.5V
and 0V
A =
2.5 V B C L C
= 0 V
Transmission gate combines the best of both devices by placing an NMOS in parallel with PMOS (most popular approach). Also make circuit static.

12. Resistance of Transmission Gate
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Resistance of Transmission Gate
It is therefore acceptable that the equivalent on-resistance of Transmission Gate has a constant value (8K in this case)

13. Pass-Transistor Based Multiplexer
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Pass-Transistor Based Multiplexer S S
VDD
GND A S S B

14. Transmission Gate XOR When B=1, M1/M2 inverter, M3/M4 off, so F=AB
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Transmission Gate XOR A B F M1 M2
M3/M4
When B=1, M1/M2 inverter, M3/M4 off, so F=AB
When B=0, M1/M2 off, M3/M4 transmission gate, so F=AB

15. Delay in Transmission Gate Networks
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Delay in Transmission Gate Networks V 1
i-1 C
2.5 i
i+1
n-1 n In R eq
(a)
(b) m
(c)

16. EE141
Delay Optimization

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Summary
Ratioed logic and pass transistor logic have their own advantages (e.g. reduced number of transistors, save area, simpler implementation, modular design, faster)
But they do not have the robustness and ease of design as the complementary CMOS (think about the XOR gate)
Therefore, use them when necessary (e.g. delay, area)
For designs with no extreme area, complexity or speed requirements, complementary CMOS is the recommended design style nowdays

18. Dynamic Logic Static/dynamic Ratioed/ratioless
Complementary/non-complementary

19. EE141
Dynamic CMOS
In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.
fan-in of n requires 2n (n N-type + n P-type) devices
Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.
requires n + 2 (n+1 N-type + 1 P-type) transistors
Dynamic logic achieved a similar result as pseudo-NMOS, but avoid short circuit and static power consumption

20. Dynamic Gate Two phase operation Precharge (CLK = 0)
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Dynamic Gate
Out
Clk A B C Mp Me
off on 1
Clk Mp
Out
((AB)+C) CL
In1
In2
PDN
In3
off
Clk Me on
For lecture
Evaluate transistor, Me, eliminates static power consumption
Two phase operation
Precharge (CLK = 0)
Evaluate (CLK = 1)

21. EE141
Conditions on Output
Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.
Inputs to the gate can make at most one transition during evaluation.
Output can be in the high impedance state during and after evaluation (when PDN off), this is fundamentally different from static complementary CMOS gate
This behavior is fundamentally different than the static counterpart that always has a low resistance path between the output and one of the power rails.

22. Properties of Dynamic Gates
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Properties of Dynamic Gates
Logic function is implemented by the PDN only
number of transistors is N + 2 (versus 2N for static complementary CMOS)
Full swing outputs (VOL = GND and VOH = VDD)
Non-ratioed - sizing of the devices does not affect the logic levels
Faster switching speeds
reduced load capacitance due to lower intrinsic capacitance (Cin)
reduced load capacitance due to smaller output loading (CL)
no Isc, so all the current provided by PDN goes into discharging CL
CL being lower also contributes to power savings

23. Properties of Dynamic Gates
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Properties of Dynamic Gates
Overall power dissipation usually higher than static CMOS
no static current path ever exists between VDD and GND (including Psc)
higher transition probabilities
extra load on Clk
PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL (inverter) equal to VTn
Small low noise margin (NML)
Needs a precharge/evaluate clock

24. Properties of Dynamic Gates
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Properties of Dynamic Gates
Main advantage of dynamic gates are increased speed and reduced area.
For low input signal, no switching occurs. So L-H delay 0!!
But this neglects the influence of precharge time (try to coincides this time with other functions to improve overall performance).
Large size of PMOS is not recommended, due to increased capacitance for H-L delay and clock
For H-L, the extra evaluation transistor somewhat slows down the gate due to extra series resistance!
Overall, the average delay is usually improved compared to static gates ( ps compared to 200ps for 4 input NAND)

25. Issues in Dynamic Design 1: Charge Leakage
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Issues in Dynamic Design 1: Charge Leakage
CLK
Clk Mp
Out CL A
Evaluate
VOut
Clk Me
Precharge
leakage sources are reverse-biased diode and the sub-threshold leakage of the NMOS pulldown device.
Charge stored on CL will leak away with time (input in low state during evaluation)
Requires a minimum clock rate - so not good for low performance products such as watches (or when have conditional clocks)
PMOS precharge device also contributes some leakage due to reverse bias diode and subthreshold conduction that, to some extent, offsets the leakage due to the pull down paths.
Leakage sources
Dominant component is subthreshold current
Requires a minimum clock rate!!

26. Solution to Charge Leakage
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Solution to Charge Leakage CL
Clk Me Mp A B
Out
Mkp
Keeper
During precharge, Out is VDD and inverter out is GND, so keeper is on
During evaluation if PDN is off, the keeper compensates for drained charge due to leakage.
If PDN is on, there is a fight between the PDN and the PUN - circuit is ratioed so PDN wins, eventually
Note Psc during switching period when PDN and keeper are both on simultaneously
Same approach as level restorer for pass-transistor logic
Small or large size for keeper?
Small to avoid ratio problem

27. Issues in Dynamic Design 2: Charge Sharing
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Issues in Dynamic Design 2: Charge Sharing CL
Clk CA CB
B=0 A
Out Mp Me
Charge stored originally on CL is redistributed (shared) over CL and CA leading to reduced robustness
CA initially discharged and CL fully charged.
This voltage loss can not be recovered

28. EE141
Charge Sharing V DD
Clk M p
Out C L A M a X C a B = M b C
When they are equal, it means that signal A can turn on both terminal of Ma
The exact case can be determined by the capacitor ratio b
Clk M e

29. Solution to Charge Redistribution
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Solution to Charge Redistribution
Clk Me Mp A B
Out
Mkp
Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

30. Issues in Dynamic Design 3: Backgate Coupling
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Issues in Dynamic Design 3: Backgate Coupling
The floating high impedance of the output nodes makes the dynamic circuit sensitive to crosstalk effect ( A wire routed over or close to a dynamic node may couple capacitively and destroy the state of the node)
The other equally important form of capacitive coupling is called backgate coupling (input coupled to output)
Due to capacitive backgate coupling between the internal and output node of the static gate and the output of the dynamic gate, Out1 voltage reduces

31. Issues in Dynamic Design 3: Backgate Coupling
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Issues in Dynamic Design 3: Backgate Coupling
Clk Mp
Out1 =1
Out2 =0
CL1
CL2 In
A=0
B=0
Clk Me
Due to capacitive backgate coupling between the internal and output node of the static gate and the output of the dynamic gate, Out1 voltage reduces
Dynamic NAND
Static NAND
Suppose Out2=1 when Out1=1 and In=0, if In goes high, then Out2 goes low, which couples to Out1 so that Out2 could not go all the way to GND

32. Backgate Coupling Effect
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Backgate Coupling Effect
Due to backgate coupling
Out1
Voltage
Clk
Out1 overshoots Vdd (2.5V) due to clock feedthrough
And Out2 never quite makes it to GND
Out2 In
Time, ns

33. Issues in Dynamic Design 4: Clock Feedthrough
A special case of capacitive coupling is clock feedthrough, an effect caused by capacitive coupling between the clock input of the pre-charge device and the dynamic output node.
So voltage of Out can rise above VDD. The fast rising (and falling edges) of the clock couple to Out.
The danger is to possibly cause revised-based PN junction to become forward-biased. CL
Clk B A
Out Mp Me
Danger is that signal levels can rise enough above VDD that the normally reverse-biased junction diodes become forward-biased causing electrons to be injected into the substrate.

34. Clock Feedthrough Clock feedthrough Clock feedthrough Clk Out In1 In2
Voltage
In4
Out
Clk
Time, ns
Clock feedthrough