1. 68HC11 Interrupts & Resets

2. Polling and Interrupts
CPU may need to provide support (called a service) to external devices.
How?
We can POLL devices
We can have an Interrupt system
We can have a combination of the two

3. Polling
“Ask” each device sequentially if it needs service. Note, no devices may need servicing during the poll.

4. Interrupts
Device “interrupts” CPU to indicate that it needs service.

5. 68HC11 Interrupts Interrupt system is “built-in” to 6811
Special interrupt software instructions
Special interrupt hardware resources
What needs to interrupt?
External Devices
Keyboards, Mouse, Sensors, etc.
Internal Events
Reset, Illegal Operation, User Interrupt, etc

6. Types of Interrupts Condition Code Register Maskable
The program can choose to “ignore” a maskable interrupt by setting the I bit equal to 1 in the CCR.
This is called “masking” the interrupt.
Setting the I bit = 0 “unmasks” the interrupt, allowing interrupts to be serviced.
Condition Code Register

7. Types of Interrupts Non-maskable interrupts
A program cannot choose to ignore a non-maskable interrupt.
A non-maskable interrupt is used for events that must always be serviced.
Example: Reset
A special subroutine called an
Interrupt Service Routine (ISR) is used to service the interrupt

8. Interrupt Service Routine (ISR)
ISR is a special subroutine that is designed to “service” the interrupt
Also called an “interrupt handler”
Let’s examine the interrupt process

9. Interrupt Process Interrupt occurs
CPU waits until the current instruction has finished being executed.
Note: PC is pointing to next instruction to execute
All CPU registers including the program counter (PC) and condition code register (CCR) are pushed onto stack
Interrupt bit is set (STI) to mask further interrupts.
See figure10.2
The PC is loaded with address of the Interrupt Service Routine (ISR)
- See figure 10.4
ISR is executed.
The last instruction in the ISR must be RTI.
RTI = Return from Interrup

10. Return from Interrupt
Your ISR should almost always end with a RTI instruction
RTI – Return from Interrupt
What does RTI do?
Pulls all registers from stack.
The I bit in the pulled CCR is clear,
so interrupts are enabled.
PC contains address of next instruction
Continues interrupted program

11. LED Circuit Example
Switch
Light On
Light Off

12. 68HC11 LED Example Polling Example
Pseudo-code (Polling)
* Use PA0 for Input, PA6 for output
Configure PortA ;
Repeat
IF(PA0=0) then
PA6=0 ; Turn LED OFF
Else
PA6=1; Turn LED ON
EndIF
Until Forever

13. 68HC11 LED Example Interrupt Example
Pseudo-code (Interrupt)
* Use PA6 for output
Configure PortA ;
Enable Interrupts
Execute any program
ISR: *Executed only when interrupt occurs
Read PortA
If PA0=0 Then LED=0 Else LED=1
Return from Interrupt

14. Interrupt Control
WAI
RTI
CLI
SET

15. Local VS Global Control
Global control is the process of controlling an entire class of interrupts with a single bit.
I bit in CCR is a global control. It masks all maskable interrupts.
Local Control bits provide individual control of each interrupt within the class.
When the I=0 the each individual interrupt source can be enabled or disabled using local control bits.

16. Interrupt Service Routine
Where is the address to the ISR?
The address of the ISR is stored in the Interrupt Vector Table.
68HC11 Interrupt Vector Table
$FFC0-$FFFF (2 bytes for each interrupt)
Example:
Reset “interrupt” vector is at address
$FFFE:$FFFF

17. 68HC11 Interrupt Vector Table
Serial Systems (SCI and SPI)
SCI: $FFD6:$FFD7
SPI: $FFD8:$FFD9
Timer System
IRQ and XIRQ Interrupts
IRQ: $FFF2:FFF3
XIRQ: $FFF4:FFF5
Software Interrupts
SWI, Illegal Opcode Fetch
SWI: $FFF6:FFF7
Hardware Interrupts
COP failure, Clock Monitor Failure, Reset

18. IRQ and Reset IRQ Vector :$FFF2:FFF3 Reset Vector: $FFFE:FFFF
Software Example
IRQ and Reset
IRQ Vector :$FFF2:FFF3
Reset Vector: $FFFE:FFFF

19. Nonmaskable Interrupts
Nonmaskable interrupts cannot be ignored
Several types
External hardware interrupts
Internal hardware interrupts
Software interrupts

20. 68HC11 Nonmaskable Interrupts
Reset
External hardware interrupt
Reset Pin (Active low)
Vector: $FFFE:FFFF
SWI Instruction
Software interrupt
Vector: $FFF6:FFF7
Computer Operating Failure (COP)
Internal hardware interrupt
Watchdog timer
Vector: $FFFA:FFFB

21. 68HC11 Nonmaskable Interrupts
Illegal Opcode Trap
Software Interrupt
Vector: $FFF8:FFF9
Nonmaskable Interrupt Request (XIRQ)
External hardware interrupt
XIRQ Pin
Vector: $FFF4:FFF5

22. 68HC11 XIRQ Interrupt Nonmaskable Interrupt Request (XIRQ)
External hardware interrupt
On reset, the XIRQ interrupt is disabled, the programmer must enable it by clearing the XIRQ bit.
E.g. During the boot process
Once the XIRQ is enabled, the programmer cannot disable it
E.g. Users cannot turn this off!!!!
XIRQ Pin
Vector: $FFF4:FFF5

23. 68HC11 Interrupt Instructions
SEI: SEt Interrupt mask: Set I bit to 1
Disables (masks) all maskable interrupts
CLI: CLear Interrupt mask: Reset I bit to 0
Enables (unmasks) all maskable interrupts
SWI: SoftWare Interrupt
Generates software interrupt
WAI: WAit for Interrupt
Pushes all registers onto stack
Places CPU into wait state
Interrupt will “wake-up” controller
RTI: Return from Interrupt
Pulls all registers from stack
Executes interrupted program

24. Polling
“Ask” each device sequentially if it needs service. However, no devices may need servicing.

25. Interrupts
Device “interrupts” CPU to indicate that it needs service.

26. Multiple Devices
Use Interrupt to indicate that a device needs to be serviced.
ISR then “polls” each device to determine who needs service

27. Multiple Devices
May need external logic to “arbitrate” devices

28. Priority with Multiple Devices
What if two devices request an interrupt at the same time?
Use a “priority” scheme to determine which device gets serviced first.
68HC11 Built-in Priority Scheme
IRQ
Real Time Interrupt
Timer Input Capture – 1-3
Timer Output Compare – 1-5
Timer Overflow
Pulse Accumulator
Serial Interface
Can be changed via the HPRIO ($103C) register