1. Digital HCAL readout studies
1 - Readout for Prototype
(Laboratoire Leprince-Ringuet-IN2P3)
2 - Readout for a large scale detector
(SEL-SEE - Seoul National University)
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

2. Studies for the prototype
Design
Test
Construction
of a test set-up for the readout of a digital HCAL
WARNING
The LLR electronic group working on the project
A.Karar, F.Dohou, A.Montgermont
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

3. CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02
Two examples of RPC as active element
by courtesy of Vladimir Ammossov
Pad size
1x1 cm2
Pads outside
Gas gap thickness
1.2 mm
Gas mixture
TFE/N2/IB 80/10/10
First measurement
Pads inside
Efficiency to mip > 98%
Signal on 50 W : 1-3 V
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

4. CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02
Signal output of the RPC
Signal (on 50 W)  1 V
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

5. CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02
Possible readout scheme for a VFE 64 channel chip
Requirements
Thin PCB (1mm)combining pads and circuitry
Thin packaging, TQFP 1 mm
Low power dissipation ~ 1 mW/ch
Reading the chips through
a token ring
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

6. CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02
Scheme of the test set-up
Test all these idea with readout for cosmic
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

7. CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02
The test set-up
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

8. CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02
The FPGA part
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

9. CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02
The conditioning circuit
RPC - FPGA interface
The requirements
Current to voltage conversion
Pulse stretching
Digital output (CMOS compatible)
Low input impedance
Overvoltage protection of FPGA
Low power consumption
Detecteur = source de courant , dans R1 et R2 circule le meme courant, donc en fonction de Q1 et Q2 le signal peut meme etre amplifier
RPC conditioning
by current mirror circuit
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

10. CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02
Results with Current Mirror circuit
Output signal
VOLT
Ici le signal vient d’un cristal et d’un PM, en fait avec une RPC cela devrait etre plus facile
Input signal
microseconde
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

11. CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02
The FPGA-DAQ on PC
On MATLAB
All readout chain
is ready
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

12. Design of Readout Electronics for digital HCAL on Linear Collider
Jaehong Park, Taeyeon Lee, Jinho Sung,
Sanghyun Min, Donghwan Lee
System Electronics Laboratory
School of Electrical Engineering
Seoul National University, Seoul, Korea
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

13. CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02
System configuration
Input signal condition
System configuration
Typical for RPC
Rise time: 3ns
Width: 10~15ns
Amplitude: 300~500mV
Readout
electronics
Control
Data
Detector
64 signals
Control station
1cm
Pad
8 x 8 = 64 pads
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

14. Readout Electronics Design
Functional Block Diagram of Readout
FPGA
DAC 1 2 64 65 76
Bunch
crossing
counter
256
Serializer
Serial_data
Empty
DAC
Threshold
Comparator
Pad
FIFO
76 x 256
Count pulse
Clear
Loader
WCLK, WEN/
Serial
link
CLK
Control LE
FF/
CLK, Selector input
RCLK,REN/ Q
EF/
DAC input
Reset/
Retrieve
Counted
Connector
Comparators
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

15. Simulation Results of FPGA
Load Dead pixel configuration
Set DAC
Command: RESET
Command: LOAD CFG
DAC DATA
MASK DATA
Command: SET DAC
Upper 2bit
Lower 8bit
Update DAC

16. Simulation Results of FPGA
Measure
Retrieve
Command: MEASURE
Measuring Process
Command: RETRIEVE
Bunch Cross Counter 12bit
Comparator Data 64bit

17. CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02
Test Circuit Design
Test Circuit
Check out the functions of Readout Electronics
Test circuit size: 9x9 cm2
FPGA
DAC
Connector
Comparators
Component side
Solder side
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02

18. Conclusion At least, one conclusion NOW
All the pieces of the puzzle have been
Designed
Built
Tested
FPGA with in front,
a Current Mirror circuit (LLR) or ADC+discriminator (SELSEE-SNU)
We are ready to read the prototype very soon for a RPC-type signal
At least, one conclusion NOW
The possibility to design a thin, simple, cheap
electronic readout for the digital HCAL,
has been demonstrated
CALICE collaboration J-C. BRIENT (LLR) JEJU-LCWS02