1. Virtual Memory: the Page Table and Page Swapping
CS/COE 1541 (term 2174)
Jarrett Billingsley

2. Class Announcements How was “break”? HW4 will be out Wednesday.
Thought I’d push it back cause of the project pushback.
You still have until tomorrow night to turn in Project 1.
…for a 20% late penalty.
Going to re-cover some PT and TLB stuff from the last lecture.
That was a pretty anemic presentation.
3/13/2017
CS/COE 1541 term 2174

3. Just to recap… Cache Term VMem Term Block Page Miss Page fault
VMem: virtual memory
PMem: physical memory
VM: virtual machine
VA: virtual address
PA: physical address
PT: page table
VMem goals:
Protection
Collaborative execution
Relocation
Also, to present larger memory space than physically available – but not as much of a focus these days.
Cache Term
VMem Term
Block
Page
Miss
Page fault
Code
Memory
Process 1
0x8000
0xFFFF
Process 2
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CS/COE 1541 term 2174

4. The Page Table
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CS/COE 1541 term 2174

5. The yellow pages of memory
The page table (PT) is a “directory” which maps from VAs to PAs.
It’s indexed by the VA page number.
Each page table entry (PTE) has some familiar-looking info…
The valid bit says whether or not this is a valid virtual page.
The dirty bit says whether or not it has been written to.
The reference bit says whether the data in this page has been read or written recently (more on this later).
Finally, there’s the PA page mapping.
VA page# V D R
PA page# - 1 2
0x852F 3 4
0x24E 5
0x16244 …
...
3/13/2017
CS/COE 1541 term 2174

6. Hey, don’t touch that! Okay, there’s more to it than that…
Each PTE also has protection.
This says if a page can be:
Read
Written
eXecuted
This is important not only for program stability, but to avoid attacks by malware!
If you make the stack non- executable, that makes it much harder for malware to exploit your programs. V D R
PA page# - 1 2
0x852F 3 4
0x24E 5
0x16244 …
...
Prot - RX R RW
...
3/13/2017
CS/COE 1541 term 2174

7. Whose pages?
Given that each process has its own VMem space, what would happen if we used one PT?
Each process needs its own PT.
We solve this by having a PTR (page table register) to point to the current PT.
Code
Memory
Process 1
0x8000
0xFFFF
Process 2
Process 1 V D R
PA page# P …
...
0x8000 1
0x590B RX
Process 2 V D R
PA page# P …
...
0x8000 1
0x6AD0 RX
3/13/2017
CS/COE 1541 term 2174

8. How big is the PT?
32-bit addresses with 4KiB (212 B) pages means 220 (1M) PTEs.
64-bit addresses with 4KiB pages means 252 (4 quadrillion) PTEs.
We can use hierarchical page tables as a sparse data structure.
Address
10 bits (“directory”)
10 bits (“table”)
12 bits (“offset”)
index...
index...
PA! V D R
Table Addr …
... 1
0004C000 V D R
Page Addr P …
... 1
03BFA000 RX
PTR
3/13/2017
CS/COE 1541 term 2174

9. How many damn memory accesses do we need???
How it works
Let’s do lw $t0, 16($s0)
Since the cache uses PAs…
PA! V D R
Table Addr …
... 1
0004C000 V D R
Page Addr P …
... 1
03BFA000 RX
PTR
Cache
miss…
hit!
CPU
How many damn memory accesses do we need???
3/13/2017
CS/COE 1541 term 2174

10. The TLB

11. It just never ends Why not have a cache dedicated to PTEs?
We call this the translation lookaside buffer (TLB).
I don’t know why.
Each block contains 1 or more PTEs.
On a hit…
Hey, instant VA -> PA translation!
On a miss…
Uh oh.
Is it just that the PTE we need isn’t cached (a TLB miss)?
Or is it that it’s a page fault – an invalid address?
Which one do you think is more likely?
VA Page V D R
Page# P …
00008 1
03BFA RX
3/13/2017
CS/COE 1541 term 2174

12. TLB Performance
We can’t even access L1 cache without doing translation.
So how fast does the TLB have to be?
Fast.
TLBs have to hit in a single cycle or less.
Therefore:
The TLB is small (hundreds of blocks).
Set associativity to reduce miss rate without making it too slow.
Random replacement for speed (no time for LRU!).
Write-back for less bus traffic.
Only the valid/dirty/ref bits have to be written anyway!
3/13/2017
CS/COE 1541 term 2174

13. Switching processes
When you switch from Process 1 to Process 2… are the TLB and cache entries valid anymore?
NOPE.
We could flush (invalidate everything) the TLB and cache, but process switches happen a lot.
Instead what we do is add a process identifier to each cache/TLB entry, and another register to hold the current process.
That way we can keep the cache/TLB full, and only the currently-running process’s entries will be treated as valid.
Isn’t this fun? ;D
3/13/2017
CS/COE 1541 term 2174

14. Page Swapping
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CS/COE 1541 term 2174

15. Capping again…
Page Swapping, or paging, means putting memory pages into nonvolatile storage.
That is, we’re using RAM as a disk cache.
It lets you:
Pretend you have more physical memory.
Run more programs at once.
Hibernate the system (make a “save state”).
Randomly access very large files.
But mechanical hard drives have high latency, though pretty good bandwidth.
This leads to large (>4KB) pages, fully-associative mapping, LRU replacement with write-back, and write buffers.
3/13/2017
CS/COE 1541 term 2174

16. Page Faults aren’t always an error
In VMem, a page fault means that the program is performing an invalid access.
Either it’s using an invalid memory address…
Or it’s trying to do something illegal when using a valid address.
e.g. trying to execute a non-executable page.
But page faults are handled by the OS, in software.
So we can do whatever we want on page faults!
3/13/2017
CS/COE 1541 term 2174

17. A cache, stomping on your face, forever.
We can treat invalid PTEs specially: we can say that they point to a block on the disk instead of memory.
VA page# V D R
PA page# P …
...
0x7FFE
<3354> RW
0x7FFF
<9218>
0x8000 1
0x590B RX
Memory
3/13/2017
CS/COE 1541 term 2174

18. Handling page faults
When a page fault occurs, the OS can inspect the faulting process’s PT to see if it needs to “page in” a block from the disk.
And just like with the cache…
We may have to evict a physical memory page first.
And if the page is dirty, we have to write it to disk.
The OS reserves a part of the disk as swap space – a special area used only for storing blocks from memory.
So page faults are slow.
Usually the OS will put your process on hold while handling the fault, and come back to it when the transfer is complete.
3/13/2017
CS/COE 1541 term 2174

19. Hibernation and Large File Access
This leads very naturally to two useful concepts:
Hibernation is performed by simply paging every page to the swap space, and then shutting down.
Then when the OS boots again, it pages them all back in, and resumes exactly where it left off.
Large file access can be performed by “mapping” a file into a process’s virtual address space.
Then the process accesses the file by accessing memory.
When a page fault occurs, the OS handles bringing in the page!
The OS can also evict pages of the file that you haven’t used.
3/13/2017
CS/COE 1541 term 2174