1. Christophe Beigbeder PID meeting
Young researcher project submitted by Nicolas on PID project. - > Still waiting news from ANR !
Caen Physics Lab has “ officially “ joined the collaboration for their participation in the SCATS TDC. The 2 engineers could be called “ associate members “.
Christophe Beigbeder PID meeting
Mai 31th 2011

2. Christophe Beigbeder PID meeting
Orsay
Mezzanine : -8 channels CFD like + Amp for charge measurement : the design is ongoing with a new LPNHE
We are building the PM setup thanks to the expertise of Veronique ‘s team.
We plan to test the performance of the mezzanine with a wave catcher board and its software : time ( discriminator ) and charge are acquired to measure the walk
Mother board : ADC + SCATS + FPGA
- Associate time & charge
- Data packing.
- Bus interface : USB, GVbus
-> equips both PM test Orsay and CRT
Christophe Beigbeder PID meeting
Mai 31th 2011

3. SCATS : functional synopsis
Christophe Beigbeder PID meeting
Mai 31th 2011

4. Christophe Beigbeder PID meeting
Layout synopsis
Layout done .
Simulation post layout done for the Ram. To be done for the 2 channel block.
Layout on going
Simulation post layout will follow
Layout on going
Post synthesis problems to be fixed
Simulation post layout will follow
Christophe Beigbeder PID meeting
Mai 31th 2011

5. Christophe Beigbeder PID meeting
SCATS : Digital part
The layout of Scats ( digital part ) gives precious information for post layout simulations and for detecting timing problems and underwent a complete fault coverage. We need to simulate RAM with specs extracted from the layout simulation
Write pulse min width: 500 ps Read pulse min width : 1ns Rd to output : ~ 3 ns Set up and Hold time : ~ 200 ps
These parameters are integrated in Verilog ram simulation model. Post layout simulation possible with a very performant simulation test bench
Scats_digital layout 948µm x 933 µm
Christophe Beigbeder PID meeting
Mai 31th 2011

6. Christophe Beigbeder PID meetingW0 W1 W7
En Fifo1
B<0>
B<1> 16
Elementary memory cell
B<15> 32 W0 W1 W7
B<0>
En Fifo2
B<1> 16
B<15>
AMS CMOS 0.35µm technology
1000µm
120µm
Christophe Beigbeder PID meeting
Mai 31th 2011

7. Christophe Beigbeder PID meeting
Each of the following blocks must not exceed a height of 50µm to match topological design constraints
Asic_fifo_control block of Scats : 591µm x 50µm
Pcsm block of Scats :131µm x 50µm
Christophe Beigbeder PID meeting
Mai 31th 2011

8. Two channels block layout
32-bit wide * 8-word long FIFO
Fine Time measurement: DLL
440µm
3300µm
Christophe Beigbeder PID meeting
Mai 31th 2011

9. Christophe Beigbeder PID meeting
Electronics is split in two parts :
one directly mounted on the PM base receiving the PM signal and processing it with TDC/ADC
the other one concentrates and pack all the channels to send data to the DAQ
Electronics on the detector :
Mechanical constraints
->FBLOCK design
Thermal constraints
-> 200 w per crate to be confirmed
Power distribution issues .
->Could use rad hard power supply like LHCb
Cables and links
Only one link per sector
Christophe Beigbeder PID meeting
Mai 31th 2011

10. Christophe Beigbeder PID meeting
FBLOCK
PCB FE boards plugged into “crate slots”
PCBs and backplane(s) partitioned in columns could be removed “completely”
Christophe Beigbeder PID meeting
Mai 31th 2011

11. Christophe Beigbeder PID meeting
Conclusion
Setup for PM tests is on tracks
We started the design of the mezzanine board
Version with commercial components (CFD like) .
Architecture has to be study depending on :
Mechanical constraints
Backplane, cooling and power issues
SCATS : layout of the 16 channel , simulation post synthesis and post layout are ongoing Submission still foreseen for July
And happy birthday to Daniel !
Christophe Beigbeder PID meeting
Mai 31th 2011