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ISA System Architecture
홍 원 의
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Contents ISA Bus Structure Types of ISA Bus Cycle
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Memory & I/O Space μProcessor Memory / IO address bus data bus
8086/8088 mem : 1M I/O : 64K A[19:0] D[7:0] D[15:0] 80286 mem : 16M A[23:0] 80386 ~ Pentium mem : 4G A[31:0] D[31:0]
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80286 System Engine
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8-bit portion 0Vdc RESET +5Vdc IRQ2/IRQ9 -5Vdc DRQ2 -12Vdc NOWS#
SMWTC# SMRDC# IOWC# IORC# DAK3# DRQ3 DRQ1# REFRESH# BCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DAK2# TC BALE OSC B A01 B A02 B A03 B A04 B A05 B A06 B A07 B A08 B A09 B A10 B A11 B A12 B A13 B A14 B A15 B A16 B A17 B A18 B A19 B A20 B A21 B A22 B A23 B A24 B A25 B A26 B A27 B A28 B A29 B A30 B A31 CHCHK# SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 CHRDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
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16-bit portion M16# IO16# IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DAK0# DRQ0
+5Vdc MASTER16# 0Vdc D C01 D C02 D C03 D C04 D C05 D C06 D C07 D C08 D C09 D C10 D C11 D C12 D C13 D C14 D C15 D C16 D C17 D C18 SBHE# LA23 LA22 LA21 LA20 LA19 LA18 LA17 MRDC# MWTC# SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15
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Address Bus SA[19:0] LA[23:17] SBHE# (from microprocessor)
microprocessor’s latched address bus address appears on the SA at rising edge of BALE and latched at trailing edge of BALE LA[23:17] buffers upper bit of microprocessor’s address bus SBHE# (from microprocessor) signals that the upper half of the data bus, D[15:8], will be used to transfer a byte
![Address Bus SA[19:0] LA[23:17] SBHE# (from microprocessor)](http://slideplayer.com./slide/13089519/79/images/7/Address+Bus+SA%5B19%3A0%5D+LA%5B23%3A17%5D+SBHE%23+%28from+microprocessor%29.jpg "microprocessor’s latched address bus. address appears on the SA at rising edge of BALE and latched at trailing edge of BALE. LA[23:17] buffers upper bit of microprocessor’s address bus. SBHE# (from microprocessor) signals that the upper half of the data bus, D[15:8], will be used to transfer a byte.")
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Data Bus SD[7:0] the lower data path during transfers with both 8-bit and 16-bit device SD[15:8] the upper data path during transfers with 16-bit device
![Data Bus SD[7:0] the lower data path during transfers with both 8-bit and 16-bit device. SD[15:8]](http://slideplayer.com./slide/13089519/79/images/8/Data+Bus+SD%5B7%3A0%5D+the+lower+data+path+during+transfers+with+both+8-bit+and+16-bit+device.+SD%5B15%3A8%5D.jpg "the upper data path during transfers with 16-bit device.")
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ISA Command Lines Asserted
Bus Cycle Definition decoded by bus control logic μP’s Bus Cycle Definition Signal M/IO# S0# S1# Bus Cycle Type ISA Command Lines Asserted Interrupt Acknowledge none 1 I/O Write IOWC# I/O Read IORC# Halt or Shutdown Memory Write MWTC# or SMWTC# Memory Read MRDC# or SMRDC#
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Bus Cycle Definition SMRDC#
(from system board logic) SMRDC# signals during memory read cycle that addresses the lower 1MB memory address space 8-bit memory card should use this as an enable to decode the memory address on the address bus prevents 8-bit memory cards from being selected when a memory address greater than 1MB is on the bus
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Bus Cycle Definition SMWTC#
(from system board logic) SMWTC# signals during memory write cycle that addresses the lower 1MB memory address space 8-bit memory card should use this as an enable to decode the memory address on the address bus prevents 8-bit memory cards from being selected when a memory address greater than 1MB is on the bus
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Bus Cycle Definition IOWC# IORC# MRDC# MWTC#
(from system board logic) IOWC# signals during I/O write bus cycle IORC# signals during I/O read bus cycle MRDC# signals during memory read bus cycle 16-bit memory card should use this as enable when decoding the memory address on the address bus MWTC#
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Bus Cycle Timing BCLK derived from the input clock to the system board μP 80286: 8MHz (double freq clock input CLK2) / 2 = 8MHz to synchronize to each bus cycle generated by μP, the BCLK generator on the system board monitors the S0# and S1# resynchronized at the leading edge of every bus cycle 1 cycle of BCLK : duration of address time or data time
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Bus Cycle Timing BALE CHRDY NOWS#
rising edge: μP’s address bus A[19:0] is gated through the address latch and through the bus control logic onto the SA[19:0] falling edge: the address latch and bus control logic hold the current address on the SA bus during the current bus cycle CHRDY deasserted when an ISA expansion board requires more wait states than would normally be supplied NOWS# when ISA expansion board requires zero wait states
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Device Size M16# tells the data bus steering logic that the addressed memory device is capable of communicating over both data paths. IO16# provides same function for 16-bit I/O expansion devices as the M16# signal provides for 16-bit memory devices.
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DMA DRQ[3:0], DRQ[7:5] DAK#[3:0], DAK#[7:5]
DMA request for channel 0 through 3 and 5 though 7 DRQ4 is used by the slave 8237 DMA controller DAK#[3:0], DAK#[7:5] DMA acknowledge for channel 0 through 3 and 5 through 7 DAK4# is used by the master 8237 DMA controller
![DMA DRQ[3:0], DRQ[7:5] DAK#[3:0], DAK#[7:5]](http://slideplayer.com./slide/13089519/79/images/16/DMA+DRQ%5B3%3A0%5D%2C+DRQ%5B7%3A5%5D+DAK%23%5B3%3A0%5D%2C+DAK%23%5B7%3A5%5D.jpg "DMA request for channel 0 through 3 and 5 though 7. DRQ4 is used by the slave 8237 DMA controller. DAK#[3:0], DAK#[7:5] DMA acknowledge for channel 0 through 3 and 5 through 7. DAK4# is used by the master 8237 DMA controller.")
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DMA TC (from DMA controller) AEN (from DMA controller) MASTER16#
asserted when the word or byte transfer count for DMA channel has been exhausted AEN (from DMA controller) asserted when one of the DMAC has been granted the buses MASTER16# assert when the 16-bit ISA bus master expansion board has been granted the buses
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Interrupts When a device on the ISA bus requires servicing by the system board microprocessor, it should assert its respective IRQ line to inform the system board microprocessor There are the ISA IRQ lines and the I/O devices that are normally used
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Error Reporting Signal & Miscellaneous Signal
CHCHK# signals an error condition to the microprocessor issues NMI interrupt REFRESH# asserted whenever the system board refresh logic is executing a DRAM refresh bus cycle OSC free-running MHz clock that may be used by ISA expansion boards
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16-bit I/O Device ISA Bus Cycle
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16-bit DMA Transfer BCLK INPUT DRQ(n) AEN DAK(n)# IORC# Read Data
SD15:SD0 INPUT OUTPUT DRQ(n) DAK(n)# TC INTR (n) High impedance (Z)
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