1. Basic Processor Structure/design

2. Here we see a very simple processor structure - such as might be found in a small 8-bit microprocessor. The various components are:
ALU Arithmetic Logic Unit - this circuit takes two operands on the inputs (labelled A and B) and produces a result on the output (labelled Y). The operations will usually include, as a minimum:
add, subtract and, or, not shift right, shift left
ALUs in more complex processors will execute many more instructions.
Register File A set of storage locations (registers) for storing temporary results. Early machines had just one register - usually termed an accumulator. Modern RISC processors will have at least 32 registers.
Instruction Register The instruction currently being executed by the processor is stored here.
Control Unit The control unit decodes the instruction in the instruction register and sets signals which control the operation of most other units of the processor. For example, the operation code(opcode) in the instruction will be used to determine the settings of control signals for the ALU which determine which operation (+,-,^,v,~,shift,etc) it performs.
Clock The vast majority of processors are synchronous, that is, they use a clock signal to determine when to capture the next data word and perform an operation on it. In a globally synchronous processor, a common clock needs to be routed (connected) to every unit in the processor.

3. Program counter The program counter holds the memory address of the next instruction to be executed. It is updated every instruction cycle to point to the next instruction in the program. (Control for the management of branch instructions - which change the program counter by other than a simple increment - has been omitted from this diagram for clarity. Branching instructions and their effect on program execution and efficiency will be examined extensively later.
Address Bus This bus is used to transfer addresses to memory and memory-mapped peripherals. It is driven by the processor acting as a bus master.
Data Bus This bus carries data to and from the processor, memory and peripherals. It will be driven by the source of data, ie processor, memory or peripheral device.
Multiplexed Bus Of necessity, high performance processors provide separate address and data buses. To limit device pin counts and bus complexity, some simple processors multiplex address and data onto the same bus: naturally this has an adverse affect on performance.

4. Internal Structure ALU Control Unit Address Bus B PC C D Data Bus E IR+1 C
ALU D
Data Bus E IR
Control Unit
ALU
CTRL Bus
FLAG A
Source : Dr. Chathura de Silva, CSE, UoM

5. Sample Program 100: Load A,10 101: Load B,15 102: Add A,B
103
104
105
Program memory

6. Before execution of 1st fetch cycleA E D C B
ALU
Address Bus
Control Unit IR
FLAG
100 +1
Data Bus
CTRL Bus
Source: Dr. Chathura de Silva, CSE, UoM

7. After 1st fetch cycle … B 101 C D E Load A,10 FLAG A Address Bus +1
ALU
Address Bus
Control Unit
Load A,10
FLAG
101 +1
Data Bus
CTRL Bus

8. After 1st instruction cycle …10 E D C B
ALU
Address Bus
Control Unit
Load A,10
FLAG
101 +1
Data Bus
CTRL Bus

9. Sample Program (Cont.)
100: Load A,10
101: Load B,15
102: Add A,B

10. After 2nd instruction cycle …10 E D C 15
ALU
Address Bus
Control Unit
Load B,15
FLAG
102 +1
Data Bus
CTRL Bus

11. Sample Program (Cont.)
100: Load A,10
101: Load B,15
102: Add A,B

12. After 3rd fetch cycle … 15 103 C D E ADD A,B FLAG 10 Address Bus +1
ALU
Address Bus
Control Unit
ADD A,B
FLAG
103 +1
Data Bus
CTRL Bus

13. After 3rd instruction cycle …25 E D C 15
ALU
Address Bus
Control Unit
ADD A,B
FLAG
103 +1
Data Bus
CTRL Bus

14. Data Flow (Fetch Diagram)

15. Data Flow* (Instruction Fetch)
PC contains address of next instruction
Address moved to MAR
Address placed on address bus
Control unit requests memory read
Result placed on data bus, copied to MBR, then to IR
Meanwhile PC incremented by 1
* CPU dependent

16. Memory Address Register (MAR)
Connected to address bus
Specifies address for read or write operand
Memory Buffer Register (MBR)
Connected to data bus
Holds data to write or last data read
Program Counter (PC)
Holds address of next instruction to be fetched
Instruction Register (IR)
Holds last instruction fetched

17. Exceptions and Interrupts
Exceptions and interrupts are unexpected events that disrupt the normal flow of instruction execution.
An exception is an unexpected event from within the processor. An interrupt is an unexpected event from outside the processor.

18. When an exception or interrupt occurs, the hardware begins executing code that performs an action in response to the exception.
This action may involve killing a process, outputting a error message, communicating with an external device, or horribly crashing the entire computer system by initiating a "Blue Screen of Death" and halting the CPU.
The instructions responsible for this action reside in the operating system kernel, and the code that performs this action is called the interrupt handler code.
After the handler code is executed, it may be possible to continue execution after the instruction where the execution or interrupt occurred.

19. Exceptions: Types
For your project, there are three events that will trigger an exception: arithmetic overflow, undefined instruction, and system call.
Arithmetic overflow occurs during the execution of an add or sub instruction. If the result of the computation is too large or too small to hold in the result register, the Overflow output of the ALU will become high during the execute state. This event triggers an exception.
Undefined instruction occurs when an unknown instruction is fetched. This exception is caused by an instruction in the IR that has an unknown opcode or an R-type instruction that has an unknown function code.
System call occurs when the processor executes a syscall instruction. Syscall instructions are used to implement operating system services (functions).

20. exception handling example in c++

21. EXCEPTIONS 1. interrupts(रुकावट,बाधा,अवरोध)
--initiated outside the instruction stream
--arrive asynchronously (at no specific time)
examples:
I/O device status change
I/O device error condition
nternal error detection when should the interrupt be dealt with? as soon as possible
2. traps(जाल, फसाना )
--occur due to something in instruction stream
--arrive synchronously (while instruction is executing)
good test: if program was re-run, the trap would occur in precisely the same place in the code.
bad opcode
arithmetic overflow
attempt to access privileged or unavailable memory