1. Edinei Santin CERN, April 27th 2017
Periphery DACs Scans
Edinei Santin
CERN, April 27th 2017

2. Preliminary notes Software used for the measurements:
Boards used for the measurements:
CaR board #4
CLICpix2 board #3
Software used for the measurements:
peary v0.3+1~g79c8301
Measurements taken on evening at Vertex Lab, with no cooling/heating system on

3. Sim./meas. ouput MUX voltages
Signal
Ouput MUX voltages*
Measured with multimeter** [V]
Measured with CaR board ADC [V]
Vhdig
0.792
0.794
Vldig
0.404
0.405
Vhana
0.804
0.806
Vlana
0.402
Vtemp
0.695
0.702
Vbg
0.318
0.319
Vbpbindac
0.625
0.626
Vcpbindac
0.215
0.218
* ‘bg_tuning’ internal register set to (7)10 for all measurements
** These results were presented in the last meeting, and the multimeter used was the MTX 3293
Maximum deviation between multimeter and CaR ADC measurements is ~ 3 mV (for Vcpbindac). This proves that ADC is providing coherent data, as expected.
The environment temperature condition was not the same (we had snow forecast for this week!) as the one when multimeter measurements took place. That is why Vtemp = V now, instead of V. This means that T = ( )/-1.89 ~ 19.1 ± 2.7 °C (instead of 22.8 ± 2.7 °C).

4. Sim./meas. test pulse ‘A’ voltage, Vta, DAC scan
zoom in
Vlsb ~ 4.5 mV, as expected
Vlsb = 5 mV, limited by ADC
CaR board ADC, ADS7828, is a 12-bit A/D converter with VREF = V set externally through a voltage reference, REF5040, on the CaR board. Hence, it can measure a signal with an accuracy no better than VREF/212 = 1 mV (assuming the ADC follows datasheet recommendations, particularly concerning VREF & VDD (!), for achieving the specified gain, offset, linearity errors and noise!).

5. Measured ‘voltage’ DACs scans
Same level of matching between simulated and measured results is achieved for all ‘voltage’ DACs, and it is comparable with the Vta DAC shown in the previous slide

6. Measured ‘current’ DACs scans
Same level of matching between simulated and measured results is achieved for all ‘current’ DACs, and it follows the matching trend of the Vta DAC shown previously

7. Measured special ‘current’ DACs scans
Same level of matching between simulated and measured results is achieved for all ‘current’ DACs, and it follows the matching trend of the Vta DAC shown previously

8. Measured special ‘voltage’ DACs scans
zoom in
256
16-bit segmented DACs for threshold and test pulse injection.

9. Measured special ‘voltage’ DACs scans
zoom in more
16-bit segmented DACs for threshold and test pulse injection. Designed Vlsb = 0.5 mV, and the ADC on CaR board limits the accuracy of the measurement to 1 mV. Accordingly, we cannot extract DNL, INL and other performance parameters for these DACs.

10. A way to decrease the Vlsb of the CaR board ADC
VREF = 1.2 or V set by a R divider
VDD=4.5V !?

11. Software change to accommodate workaround
CAR_VREF_4P0 = 1.2 or 1.024V

12. Conclusions
Measured and simulated results so far match quite well (deviations whithin expectations)
Next steps (~ 5 weeks until next submission!):
Pixel threshold scans (and threshold calibration)
Test pulse injection
Matrix readout
...

13. Thank you for your attention!