1. of the High Voltage part of the on-detector electronics
Phase II upgrade
of the High Voltage part
of the on-detector electronics
François Vazeille
(LPC Clermont-Ferrand)
Preliminary requests about
the radiation hardness
HV Distributors
HV Dividers
Conclusion 1

2. Preliminary requests about the radiation hardness
The radiation tolerant Tilecal electronics was a key point for LHC:
it will be the same … but worst for SLHC!
No development on the on-detector electronics should start
before a deep approach of the radiation levels and rules.
 2 major requests:
 A request to CERN
… to provide collisions!
Radiation probes should provide the true levels of radiations at any locations:
- Tuning of the simulations made till now.
- Realistic estimates of the safety factors for LHC.
even though some scaling should be done going from 10 TeV to 14 TeV.
 A request to ATLAS
… to define very early (in fact: NOW) the rules
that will be applied to the electronics.
Choices of electronics design/components and radiations tests to do…
(and not to redo them several times because of lack of information). 2

3. HV Distributors
No clear R&D at this moment, because of 3 main reasons:
- Is it sure that the HV regulation will stay on-detector?
- What will be the final dimensions of Drawers?
- The final approach of the design of the HV part must be made
in close collaboration with the read-out and the LVPS parts.
 Nevertheless, taking benefit from both the Tilecal experience
and the technical progresses
Some baseline assumptions or ideas can be proposed for on-detector HVs.
 Brief reminder of the justifications of the present ATLAS design.
The best performances: HV regulation placed close to the PMTs.
• Good regulation (<< 0.5 V).
• Low noise (no pick-up in long HV cables).
A “low cost”: no commercial solutions of HV Distributors (Drawers)
and HV Sources (USA15).
Study in progress of the true working over a long period of about channels
from the ATLAS runs in 2008. 3

4.  Reminder about the Tilecal set-up (Slides shown on February 2008 meeting).
… The individual regulation loop
Tilecal in-situ regulation
Based on one
Optocoupler chip/channel
Use of an external HV
(common to 24 Channels)
located in USA15 room
2 HV resistors
HV out
Opto
coupler
From
DAC
Loop working stand-alone
once the DAC value is set
by the user
via the DCS
(…even though
the DCS is lost
or if the HV Micro is dead)
From
HV Source
2 HV transistors 4

5. HV Distributors of Super-Drawer
… The general set-up in the pit
 2 main elements:
- HV Source (USA15)
- HV Distributors (UX15)
USA15
LVCAN PC HV PC
+ Associated elements and connections:
- CANbus and LVCAN PS (and LVCAN PC)
- DCS: HV PC + CAN interfaces
- fLVPS HV
Source
LVCAN
Patch P
Internal HV Bus
Flex Bus
External HV bus
Internal
HV Opto
External
HV Opto HV
Micro
fLVPS
HV Distributors of Super-Drawer
(6 cards/Super-Drawer)
Daisy
chain 5

6. 6
 Weak points of the present ATLAS design (Robert and François)
- Optocouplers and EEPROMs: rather sensitive to radiations.
- HV resistors (Low cost HV resistors: 10 times cheaper): restricted reliability.
- HV transistors: sensitivity to short-circuits (from mistakes) and striking.
Printed board design/making:
▪ Sensitivity to humidity: the insulation could go from 1 (1 KV spec.) to 1.5 mm.
▪ Optimization of the ground tracks/HV or /signal tracks: could be better.
Electronic HV switches: Fast current change when switching HV On/Off:
not well supported by HV Source.
Measures of individual input low voltages: not reliable indication if out of range.
Possible switching of 12 channels altogether (for cost reasons):
not individual switching in case of a single faulty channel.
- Several kinds of boards and induced interconnections: failure risks.
3 different input Low Voltages (+ 5 V and ± 15 V… and 5 for the Read-out):
8 different bricks in total in the fLVPS.
- No direct hardware link with fLVPS in case of a requested fast switching.
Low speed of CANbus and not the best choice for HV part (8 bytes frames).

7.  Possible changes in the HV upgrade.
Hypothesis: always a use of COT components in the upgrade
and not radhard components too much expensive,
except if radiations were well above expectations.
Reduction of number of input Low Voltages:
 a minimum of 2 voltages such as ± 5 V, because of 2 reasons
- No possibility of controlling negative HVs without using a negative LV.
- Positive LV for the logics.
with a possible LV regulations on HV cards (CERN regulators?).
No use of boards having not usual sizes or shapes:
- Stiff Bus boards: large dimensions 131 x 9 cm2.
- Flexible Bus boards: fragile and difficult design.
 Only HV OPTO cards (2/Drawer like MB) directly connected to HV Dividers.
New location and new choice of MICRO chip:
 Location on the HV OPTO board.
 Choice of a standard ATLAS controller (New version of ELMb?).
 Each Drawer could be fully independent (if it the same for the Read-out side)
or a dedicated board could act as an Interface with the external world. 7

8. Optical link replacing CANbus?
 Not obvious:
- Low data stream for a fiber system.
- Communication working in both directions (Drawer  DCS).
unless fibers sharing other parts of Drawers? Likely not obvious.
In any case: we must follow the ATLAS choice (Urgent!) of the DCS system.
 Other changes listed in weak points
New HV resistors (more expensive) …
and for ever no mistakes due to bad manipulations or other systems
killing HV Transistors.
- Printed board making and grounding optimization.
Individual HV switches: both a cost aspect of the Drawers
and induced modifications of HV Sources (One switch consumes 100 µA
 5 mA for a Super-Drawer): is there another way to switch off?
Removal of EEPROMs: 3 solutions to store calibration parameters
• No calibration parameters on cards, but stored in DCS data base.:
not the best for MobiDICK.
• Parameters inside FLASH memory of µC.
• Dedicated FLASH memories on cards
(But not easy to find small size memories).
Suppression of temperature probes (All, some?)
and suppression of measures of input voltages?: Likely no. 8

9.  What type of regulation loop?
Problem: no other commercial Optocoupler able to accept such a high HV!
 We must likely keep them (With a 400 V range).
- Suppress one of the 2 HV resistors (To be tested … like other ideas).
- Use one DAC (Lower cost now) and one ADC/channel (smaller size now)
 Shorter tracks  signal/noise improved.
- Implement noise killers on every channel.
 More components on unique cards (OPTO cards).
Why not to make use of Microelectronics for part of them ?
… even though it is less thrilling than developing a 80 MHz ADC! 9

10. TID NIEL  True radiation levels and realistic safety factors?
From the radiation tests made on the present HV cards,
using the same requested safety factors and a scaling to the SLHC:
TID
Required
Safety factor
(3.5 on simulations)
Ultimate
SLHC:
From tests.
HV Micro bipolar
HV Micro cmos 70 14 35
HV Opto bipolar
HV Opto cmos 32
NIEL
Required
Safety factor
(5.0 on simulations)
Ultimate
SLHC:
From tests.
HV Micro 20 4
HV Opto 5
 Not so far away to the specifications: urgency of true collisions! 10

11. HV Dividers  Physical reasons of the specifications
• Linearity of jet energy measures over the whole dynamics (16 bits),
in particular at the highest energies.
+ Secondary effects: impact on resolution via the constant term b
/E = a /E + b
• The most demanding process: quark compositivity from inclusive jets.
Nb jets
QCD
Composite
Quarks
Gap / expected shape: physical effect
or detector effect?
Energy
SLHC: 10 times more high energy jets  Sensitivity to non-linearity enhanced.
At SLHC, we must recover what was performed at LHC
(Final non-linearity ≤ 2%, either ~ 1% at the PMT level)
and why not to be better (≤ 1%). 11

12.  Technical reasons: optimization of the PMT Dividers
 Divider design
- PMTs/Dividers optimized for both gain and linearity  8 dynodes.
Dividers also optimized with respect to:
• Physical noise (Pile up of Min Bias events)  to cope with induced current.
• Electronics noise  2 levels of grounds HV ground and Analog ground.
in order to have a constant noise/location along the Super-Drawer
2 ground levels 12

13.  More info on the Divider scheme
Choice of resistors
 conditioned by the current flowing through the Divider.
Empirical rules applied to build a pure resistive Divider (No active components):
• Rule #1: How to cope with pile-up?
By having a current flow 100 times larger than mean anodic current
Worst case when designing: ~2 µA  Current flow of 200 µA.
Remark: Later simulations  max current max of 576 nA (First Tile layer)
 Safety factor of 4.
• Rule #2: How to cope with very high pulses?
By having storage capacitors in last stages in order
to balance the voltage drop due to the big induced current. 13

14. Flat shape with respect to signal anodic current
 Performances
 Results on Gain variation with respect to signal (Anodic current nA)
for different levels of physical noise (Pile-up DC currents 100 nA-4 µA)
… and 4 PMTs.
PMT#
100 nA
1 µA
2µA
4µA 1
~0.2-0%
~ %
~ % ~ 2
~0%
~ %
~ %
~ % 3
~0-0.4%
~ %
~ % 4
~0-0.2%
~ %
~ %
~ %
 DC current
Flat shape with respect to signal anodic current
Mean variations with respect to physical noise, as below:
Anode current
100 nA
1 µA
2 µA
4 µA
Gain Variation
~ 0%
< 1%
~ 1%
> 2%
The Dividers fitted well the LHC specifications
even using pessimistic simulations at the design time. 14

15.  Why do we need to change the Dividers for SATLAS?
Natural ageing:
Rule of a working of hours applied to commercial products.
 It will be the case around 2017.
2. Increase of continuous current that will spoil the linearity
 MB: MB events/Crossing  230.
Barcelona simulations
Currents can reach
and go beyond 2 µA.
But it is wise to foresee
a safety factor in simulations
at least equal to 2
 Max currents max from 2 to 7.2 µA.
3. Take benefit of expert people on PMTs and Dividers…
as long as they are in the laboratories. 15

16. YES  Is there a starting solution?
Already made at LPC for LHCb among several solutions:
(The LHCb PMTs/Dividers are themselves Tilecal evolutions):
Dividers using Transistors in the last stages.
Resistive Divider: 2 µA flowing.
Divider with 2 Transistors:
400 µA flowing.
anode
anode
400 µA through the Divider is enough to cope with
an anodic current of … 100 µA. 16

17. … scheme with 3 transistors (extracted from a Note).17

18.  R&D works and planning
Test Bench PMT/Divider
 R&D works and planning
Optimization of the design: 2009
 Works: Electronics.
▪ Material: Test Bench of PMTs + 10 (or 20) PMTs.
▪ Tests with present Dividers and various anodic currents.
▪ Identical Tests with the new design(s)
and comparison,
then search and use of components (Transistors)
not too much sensitive to radiations (Use of ATLAS data bases).
Remark: Spare PMTs could be slightly different from present PMTs
 2 types of Dividers.
Radiation tests: 1st half 2010
 Works: Electronics + Mechanics (a little) + on-line. 18

19.  Refurbishing of the Test Bench of Dividers.
▪ Before October 2009:
tests of mechanics
in order to evaluate the improvements to do.
▪ October st half 2010:
- Refurbishing of mechanics.
- New on-line and Slow Control of mechanics.
▪ 2nd half 2010:
- New electronics (+ Additional works if 2 types of PMTs).
- On-line.
 Manpower for R&D provided by LPC.
 In parallel: cost estimate of the production as requested for the IMoU. 19

20. Conclusions
 No R&D is possible as longer as radiations levels and rules are not clearly defined.
If the HV regulation stays on-detector, new thoughts are proposed,
but other parts (Mechanics, Read-out, LVPS, HV Sources…) must be associated
in order to have a global approach of the on-detector electronics:
 Not later than end 2009.
Comment: Nobody and nothing at LPC will start R&D before.
An R&D is proposed on PMT Dividers to cope with the SLHC conditions,
in order to keep (and even improve) the PMT linearity and also the
constant term.
Comment: The Laser system should help too, but it is not so easy
(Works in progress in the LHC context).
In parallel, cost estimates for the IMoU will be studied for the production
of Dividers.
The production would start in 2012 or 2013, in order to fit the long SD of 2016,
and possibly several Winter SD’s before (not obvious).
Comment: steps in the order
Dividers/PMT-Dividers/PMT Blocks/Drawers/Insertions. 20