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University of Bristol: J. Goldstein, S. Seif El Nasr
CBC3: A CMS micro-strip readout ASIC with logic for track-trigger modules at HL-LHC STFC RAL: Mark Prydderch, S. Bell, M. Charrier, L. Jones, P.Murray, D. Braga† Imperial College: G. Auzinger, J. Borg, G. Hall, M. Pesaresi, M. Raymond, K. Uchida University of Bristol: J. Goldstein, S. Seif El Nasr †Now at Fermilab
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Outline Background CBC3 Features CBC3 Single Chip Testing Future work
2 Outline Background CBC3 Features CBC3 Single Chip Testing Future work Summary & Conclusion
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Outline Background CBC3 Features CBC3 Single Chip Testing Future work
2 Background CBC3 Features CBC3 Single Chip Testing Future work Summary & Conclusion
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Where to find the CBC 3 Front End Hybrid Double-Layer
2S Modules: Two-strip double-layers 7680 modules ~31M channels Front End Hybrid Double-Layer Si Strip Detectors LP-GBT & Optical VTRx 10 cm 5 cm Each 2S Module: Sensor Area ~100 cm2 16 CBCs, each reading 254 strips (127 from top & bottom sensors) 4064 Channels in total Readout both L1 triggered data & Primitive trigger data 127 Strips/CBC 8 CBCs per side DC-DC Converter CIC 1 per side Service Hybrid
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Basic 2S Module Concept R f 4 CBC Flex PCB Hybrid 500µm CF Support
CF Stiffener Bridge Silicon sensors Outer ½ Module Inner Hit Strip Correlation Window YES No Outer Sensor (Correlation Layer) Bend 1.8 4 mm Inner Sensor (Seed Layer) R f Hit Strip Particle Track (High pT) Particle Track (Low pT) High-PT tracks (Stubs) can be identified if cluster centre in top layer lies within a correlation window in R-Φ (rows) pT cut given by: module radius (z), sensor separation and correlation window
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CBC1 & CBC2 5 Common features: I2C Interface
DC – DC Converter (2.5V 1.2V) LDO for analogue power Bandgap for biases 256 deep Pipeline 40MHz Serial L1 Data Output CBC2 (2013) 254 Dual polarity channels C4 Bump Bonded Direct command inputs On-chip Test Pulse Generator with DLL Correlation logic for stub formation Cluster width veto 40MHz serial readout of Stub Data Analogue Mux for bias monitoring Front-end circuit improvements Improved DC-DC converter (CERN) 4.785 mm 4 mm CBC1 (2011) 128 Dual polarity channels Wire Bonded APV style serial command scheme Analog Test Inputs mm 7 mm CBC 1 CBC 2
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Outline CBC3 Features Background CBC3 Single Chip Testing Future work
Summary & Conclusion
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CBC3 Architecture 6 Chip ID & BG e-Fuses Analogue Front End
Nearest Neighbour Signals (NNS) 40 MHz Domain 254 vth 512 Deep Pipeline (12.8µs) + 32 Deep Buffer vth 320 MHz Domain Stub Finding & Bend Calculation Logic vth Channel Mask Hit Detect Layer Swap Cluster Width Veto Stub Gathering Logic PISO Shift Register 1 vth Overflow Band gap Bias Generator NNS Bend lookup Table L1 Counter OR 254 Chip ID & BG e-Fuses Data Packet Assembly & Transmission Stub & Triggered Data on 6 SLVS Outputs Programmable Phase 40 MHz Domain VDDA 1.0 V VDDD 1.2V LDO 320 MHz Clock 320 Mbps Serial Command input DLL 40 MHz Recovery Fast Control Test Pulse Generator DLL Configuration Registers Slow Control I2C (1 MHz)
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CBC3 Front End Changes 7 Single Polarity (electrons)
Faster Pulse Shape 3x Bias current range for larger detector capacitances New preamp regulated cascode to eliminate “Shadow effect” observed when many channels fire New postamp feedback bias scheme (not shown) Current neutral comparator Adjusted for 1V operation Eliminate common-mode effects observed when many channels fire
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Stub Logic 8 C127 Hit Det CWD Correlation & Bend Stub Gathering Logic
254 Hit Det CWD Correlation & Bend Stub Gathering Logic S127 Bend 253 Hit Det CWD Stub Address Logic Mux Layer Swap Stub Priority Logic C1 2 Hit Det CWD Correlation & Bend S1 1 Hit Det CWD 8-bit address 5-bit bend x Max 3 Stubs Correlation bit & 5-bit bend C=Correlation Layer Channel (Outer) S=Seed Layer Channel (Inner) 2 & 4 strip clusters give ½ strip Stub Address Clusters >4 Strips rejected Programmable Correlation Window C C Programmable Window Offset Bend S S
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Fast Command Interface
9 Fast Command B7 B6 B5 B4 B3 B2 B1 B0 Fast Reset 1 Trigger Test Pulse Trigger Orbit Reset Orbit Reset & Fast Reset Orbit Reset & Trigger Orbit Reset & Test Pulse Trigger 320MHzClock Fast Command Input B<7> B<6> B<5> B<4> B<3> B<2> B<1> B<0> B<7> B<6> B<5> B<4> B<3> B<2> B<1> B<0> X X X X 1 1 1 X X X X Stop Bit Sync Pattern Fast Command Sync Pattern Fast Command Recovered 40MHz Clock Fast Command (Internal) 25ns
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Outline CBC3 Single Chip Testing Background CBC3 Features Future work
Summary & Conclusion
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Single Chip Test PCB 10 Tests carried out at Imperial
Back-edge column of pads reserved for wafer probing - can be wire-bonded Interface card Additional GND bonds CBC3 All CBC3 results so far are from a wire- bonded single chip setup (chips diced from first wafer) ~Same setup used for ionizing and SEU tests
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Triggered data captured on oscilloscope
11 Triggered Data Readout Triggered data packet format Total frame length (active data) = 276 bits = ns 0 packed to 950ns MSB first channel 1 first 2 start bits 9 Bits pipe address 254 bits strip readout data 9 bits L1 count Latency error Triggered data captured on oscilloscope Buffer overflow 950 ns 320 Mbps triggered output data Frame length 950 ns Header contains the pipeline address that the data originates from + L1 counter value (reset every orbit) SLVS output driver On-chip test pulse used 2 start bits 2 test pulse bits 2 error bits 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 10 ns /div.
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Stub (trigger) data captured by DAQ
Stub Data Readout 12 MSB first Stub data packet format Stub Data <1> SLVS S1<7> S1<6> S1<5> S1<4> S1<3> S1<2> S1<1> S1<0> S2<7> S2<6> S2<5> S2<4> S2<3> S2<2> S2<1> S2<0> S3<7> S3<6> S3<5> S3<4> S3<3> S3<2> S3<1> S3<0> B2<3> B2<2> B2<1> B2<0> B1<3> B1<2> B1<1> B1<0> SYNC Flags OR254 SoF B3<3> B3<2> B3<1> B3<0> Stub Addresses Stub Data <2> SLVS Stub Data <3> SLVS Stub Data <4> SLVS Stub Bends & Flags Stub Data <5> SLVS SYNC 8 Clock 320MHz (25ns) Stub (trigger) data captured by DAQ Stub 1 address Stub 2 address Stub 3 address Stub 1 & 2 bend info 1 1 SYNC Sync pulse every 25 nsec + stub 3 bend info 1 25 ns
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Front End Pulse Shape 13 VCTH comparator iin amp. We can measure the analogue pulse shapes by sweeping the charge injection time for different comparator thresholds Simulation Measurement bm = 1 bm = 8 bm = 15 [mVolts] 2.5 fC injected [ns] Good pulse shape agreement between simulation and measurement CBC3 pulse shape duration reduced (cf. CBC2) to achieve single BX resolution Varying 4-bit beta multiplier setting gives some control over output pulse duration
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VCTH now generated by 10-bit resistor ladder DAC
14 S-curves & Channel Offsets Tuning Offset adjust Sweep global comparator threshold to generate s-curves Tune offsets to compensate for channel-to- channel differences After tuning, the channel offsets distribution has σ of ~50 electrons iin VCTH Amp. Comparator All Channel Offsets set to same value Counts VCTH now generated by 10-bit resistor ladder DAC After offsets tuning INL & DNL < 1LSB Counts VCTH [V] s = 0.3 VCTH units ~ 50 e Histogram Of S-curve mid-point values I2C value VCTH units [~mV]
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Noise, Gain & Power 15 8 Analogue Power & Inputs Digital I/O
CBC3 Single chip test board has provision to bond 8 inputs CBC3 bump-bond pads have wire- bondable finish (unlike CBC2’s C4 pads) Can make use of this to inject external charge and add external capacitance to measure noise Single-chip setup noise performance looks ok (even with a wire-bonded chip) Measured Gain 47 mV/fC with ~5% spread 350 µW/Channel Analogue 160 µW/Channel Digital Measured ENC [electrons] Simulation T=+30 T=-20 Cexternal [pF]
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Radiation Studies 16 Ionising Radiation Tests at CERN:
CBC3 irradiated to > 400 kGy No change in performance (noise, pedestals,…) Transient increase in digital current in few Mrad region falls back to pre-irradiation values at higher doses Current dominated by leakage in stub-finding logic At HL-LHC dose-rate (9 Gy/hr) & temp (-15o) the effect will be negligible (pessimistic assumptions) ~1.3% max. increase in module power consumption Interface card SEU Tests on Proton Beam at UCL (Louvain): ~15 hours of beam corresponds to ~1000 HL-LHC Detected 25 single bit flips altogether in I2C registers ~ 8x reduction cf. CBC2 Corresponds to ~1.5 bit-flips/day per chip at HL-LHC (pessimistic assumptions) Considering periodic reconfiguration vs minor changes to circuit CBC3 CBC3 at UCL proton beam
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Outline Future work Background CBC3 Features CBC3 Single Chip Testing
Summary & Conclusion
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Future Work 17 Test the CBC3 2 chip Module
Verify performance when bumped Verify nearest neighbour logic for Stubs CBC 3.1 Add invalid Stub rejection function Add Nearest Neighbour I/O test feature for wafer testing completeness Improve Triggered Data Serialiser robustness to Clock 40 DLL phase shifts Improve configuration register SEU robustness (TBC) Manufacture CBC3.1 Test CBC3.1 Production Wafers
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Outline Summary & Conclusion Background CBC3 Features
CBC3 Single Chip Testing Future work Summary & Conclusion
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Summary & Conclusion 18 Successful final full-size prototype of the new Outer Tracker ASIC CBC3 working to specification Re-designed Stub identification & new output data chain both functional Pipeline: Corrected the radiation induced effects seen on CBC2 Improved SEU performance of configuration registers 8 wafers tested with 5 sent to PacTech for bumping Some functional modifications needed for the production version Acknowledgements Thank you to all our colleagues at CERN, Bristol (UK), Gdańsk UoT (PL), KIT (DE), IPHC (FR), for their contributions mm CBC 3 5.035 mm
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