1. CCPD Hybridization AIDA-2020 Annual Meeting – WP6 DESY, 15 June 2016
Giovanni Darbo – INFN / Genova
(Genova, Milano, Trento)
Activity Supported by RD_FASE2 and HVR_CCPD INFN projects and AIDA_2020 EU
Indico:

2. CCPD – Requirements and Process
INFN-Genova is beneficiary for WP6 task 4
INFN-GE, IFAE, UNILIV
Additional INFN groups involved: Milano.
Requirements
Uniformity and repeatability of the process – we target on ~10% of capacitance variability over a pixel detector and from detector-to-detector.
Radiation tolerance
Cost effectiveness  time per chip assembly
Process considerations
Wafer to wafer processes are excluded: R/O chip are typically 12” wafers, HV-CMOS are 8”-wafers  glues seem the today option
Glue thickness cannot be 0: a minimal thickness layer must be present (3 to 5 µm?) -how to control?  have spacers limiting the minimum distance between facing chips
How to make spacers?  SU8 photo-imageable resin seems a good option
CCPD – Capacitive Coupled Pixel Detector

3. Controlled Glue Thickness
Procedure for Controlled Glue Thickness
Deposit uniform layer of SU8 photoresist on R/O chip wafer (or single chip) by spinning – tune for 5 µm layer by controlling RPM speed
Pattern pillars using lithographic process .
Spin SU-8 photoresist
Pattern pillars by mask
R/O CHIP
Glue deposition
R/O CHIP
Profile of pillars on top of a FE-I4 chip
Align & pressure
R/O CHIP
DETECTOR CHIP
Pillars
Deposition of SU8 photoresist by spinning
FE-I4 topography
Ref: AIDA-2020 kick-off meeting – June 2015
© V. Ceriale, A. Rovani, Genova, IT

4. FE-I4 chip SU8 pillar sd Side A Scan 5 Scan 4 Scan 3 Scan 2 Scan 1
Side A [µm]
Side B [µm]
Scan 1
254.40
257.04
Scan 2
257.31
257.91
Scan 3
256.77
257.83
Scan 4
256.55
257.55
Scan 5
255.97
257.23
Side A
Scan 5
Scan 4
Scan 3
Scan 2
Scan 1
Side B
FE-I4 chip
SU8 pillar
© A. Rovani & V. Ceriale - Genova

5. Glues Araldite 2011 Araldite 2020 Epotek 301-2 EPOLITE FH-5313
Master Bond
UV15DC80LV
Viscosity [Pas]
30 ÷ 45
0.15
0.22 ÷ 0.45
1.97
0.15 ÷ 0.50
Relative dielectric constant
3.4/3.2/3.2
50Hz/1kHz/10kHz ?
3.8
1kHz
4.06
100Hz
3.49
60 Hz
Loss tangent [%]
1.7/1.8/2.6
1.2
0.1
Pot life [min]
100
40÷50
480 30
Curing time [min]
60º
60º
80º
65º
UV Curing +
40 ÷ 80º
Air bubbles
Many
Some
None
To test
Rad-hard
3 MGy
CERN
TOB-NOTE 00.03
(Sep.2000)
Studied for optical properties under limited radiation doses (BaBar)
10 Mrad
Test at FNAL
Extensively Qualified by SCT
dual cure epoxy
In principle should be rad-hard

6. Experience with Glues and Gluing
Our experience tell us that:
The gluing process with spacers is something worth to explore
Glues that work (best) are low viscosity glues – liquid capillarity guarantee uniformity and bubble absence
Capillarity unfortunately has a serious issue: glue climbs at chip edges and penetrate on top and bottom of the assemblies attaching them to flip-chip head
We have found some workarounds using thin (50µm adhesive kapton) placed between flip-chip head and assembly, removed after glue is cured.
Cost effectiveness wrt bump-bonding depends on production rate: curing time is a bottleneck – assembly cannot be moved away from flip-chip machine
dual cure epoxy based system which offers a primary cure utilizing UV light along with a secondary heat curing mechanism could be the answer
Next step (on going) – dummy wafer with large (FE-I4 size) dummy chips
Capacity arrays to test uniformity of the glue dielectric layer
Wafers have been produced by FBK and spacers (pillars) are under deposition at Selex
We expect more results in a few months…

7. Dummy wafers 6 x 6”-wafers produced by FBK 30 FE-I4 size devices/wafer
1 µm passivation
1.2 µm Al1%Si metal
Standard 625 µm thick substrates
30 FE-I4 size devices/wafer
3 designs with 24 to 48 capacitors / chip

8. Dummy Assembly Test pads Top electrodes SU8 spacers Bottom electrodes
Credits: Alessandro Rovani – INFN / Genova

9. DESIGN 1
48 capacitors
3.6 5µ dielectric (er = 3.8)

10. DESIGN 2
32 capacitors
3.6 5µ dielectric (er = 3.8)

11. DESIGN 3
24 capacitors
~7 5µ dielectric (er = 3.8)

12. Parasitic Capacitance
Capacitance with 5µm glue
Upper+lower electrodes
C(1,2) = 3.61 pF
Parasitic capacitance
without upper chip
C(1,2) = 70fF
NEGLIGIBLE CONTRIBUTION
Credits: Ettore Ruscino – INFN / Genova

13. Conclusions
CCPD hybridization is (slowly) progressing – lot of work to come to a mature industrial process, cheaper than bump-bonding
Wafer-to-wafer processes seems ruled out by different size of R/O and HV-CMOS wafers
Glues are the only option (?) – still to demonstrate they fit the requirements (work in progress)
Optimization of pads design to maximize signal transfer wrt to stray capacitance
ATLAS (follows ALICE) into monolithic HV-CMOS
Is still worth to develop CCPD, or better redefine the scope of this AIDA-2020 WP?

14. Spare slides

15. Dielectric thickness (µm)  Capacitance (pF)
Credits: Ettore Ruscino – INFN / Genova
10 MHz
Dielectric
2.5um
3um
3.75um
5um
7.5um
15um
C(1,2)
6,7485
5,6125
4,4937
3,3829
2,2878
1,1613
C(3,4)
6,7267
5,5912
4,4731
3,363
2,268
1,1436
C(5,6)
6,8096
5,6761
4,5565
3,4424
2,3444
1,2124
C(7,8)
C(9,10)
C(11,12)
C5,6
C11,12
C3,4
C9,10
C1,2
C7,8
1/X
Capacitance (pF)
Dielectric thickness (um)