1. Power-Delay-Area Performance ModelIng and analysıs for Nano-Crossbar Arrays
Muhammed Ceylan Morgul, Furkan Peker and Mustafa Altun
Istanbul Technical University, Istanbul, TURKEY
{morgul, pekerf,
Emerging
Circuits and Computation Group
General Overview
Equivalent Crosspoint Capacitor Model
«Moore’s Law is nearing its end»
One of the emerging technology:
Nano-crossbar Arrays (self-assembly or lithography)
There are three types of nanoarrays:
Diode, FET and Four-terminal switch based
𝐶 𝐶𝑃_𝑒𝑞𝑣_1 ≡ 𝑉 1 − 𝑉 2 𝑉 1 × 𝐶 𝐶𝑃
𝐶 𝐶𝑃_𝑒𝑞𝑣_2 ≡ 𝑉 1 − 𝑉 2 𝑉 2 × 𝐶 𝐶𝑃
Generic 3D Model
Model’s general equation for Elmore
Test Circuit
𝒌 𝟏 =( 𝑹 𝑾_𝑪𝑷 + 𝑹 𝑶𝑵 𝟐𝑹 𝑾_𝑪𝑷 + 𝑹 𝑶𝑵 + 𝑹 𝒘 + 𝑹 𝑳 )
𝒌 𝟐 =( 𝟑𝑹 𝑾_𝑪𝑷 + 𝟐 𝑹 𝑶𝑵 𝑹 𝒘 + 𝑹 𝑳 )
𝒌 𝟑 =( 𝑹 𝑶𝑵 𝟐 𝑹 𝑶𝑵 + 𝑹 𝒘 + 𝑹 𝑳 )
𝒌 𝟒 =( 𝟑𝑹 𝑶𝑵 𝑹 𝒘 + 𝑹 𝑳 )
*ki values for test circuit
Diode
FET
Four-terminal
Power–Delay-Area Analysis with the Test Circuit
Analysis Output
FET
Diode
Four-terminal
Delay (ps)
0.15 – 0.25
0.013 – 0.024
0.04 – 0.16
Delay (ps) with 0.1fF fan-out
20 – 120
2 – 15
2 – 18
Power (uW)
0.02 – 0.16
0.01 – 0.25
0.02 – 0.3
Power 0.1fF fan-out (uW)
2.5 – 2.6
2.5 – 2.7
2.5 – 2.8
Area (nm2)
200 – 900
Power × Delay (uW × ps)
0.02 – 0.09
0.02 – 0.018
0.01 – 0.6
Contributions of Our Model
Model Part
Current Status (literature)
Contributions
(our model)
Diode crosspoint
Resistors in the crosspoint are neglected.
These resistors are taken into account since they are in the order of k due to dimension.
FET crosspoint
Crosspoint capacitor values are used in the Elmore model without calculating equivalents.
Equivalent capacitor values are calculated for Elmore ladder delay.
Nanowires and free wires
Crosstalk effect of crossing and parallel wires are neglected.
Crosstalk effect is modeled for every pair of consecutive wires.
Four-terminal switch crosspoint
Doesn’t exist in literature
Our generic model also accommodates four-terminal switch-based nanoarrays.
Performance of Logic and Memory Applications
Accuracy Test for Crosspoint Cap.
 XOR3 - FET
CCP connection type
Delay (ps)
Error %
Case-1:
5𝐶 𝐶𝑃 ≅ 𝐶 𝑤
D=1nm, pw=10nm
wire-wire - *proposed
8.31
wire-ground CCP_eqv=2CCP -[literature]
8.239
0.853
wire-ground CCP_eqv=3CCP - *proposed
8.266
0.527
wire-ground CCP_eqv=4CCP - *proposed
8.293
0.200
Case-2:
𝐶 𝐶𝑃 ≅ 2𝐶 𝑤
by changing D=10nm
4.689
2.921
1.155
Case-3:
𝐶 𝐶𝑃 as in Case-1,
𝐶 𝑤 =0
0.778
0.719
7.633
0.746
4.187
0.773
0.725
CCP_eqv values are only calculated for crosspoints which are changing states for worst-case
1-bit Full Adder Analysis
No fan-out
0,1 fF
0,5 fF
2 fF
High-to-Low Delay (ps)
0.46
15.7
77.1
307
Low-to-High Delay (ps)
1.75
60.1
293
1160
Power (1GHz) (uW)
0.212
2.71
12.7
50.2
Maximum Frequency (GHz)
452
13.1
2.69
0.67 <1!
NAND based ROM Analysis
𝑨𝒓𝒆𝒂 𝑹𝑶𝑴 = 𝟐.𝒏.𝒎. 𝑫+ 𝒑 𝒘 𝟐
n: word lines, m: bit lines, D: wire diameter , pw: pitch size
Reasonable access time intervals:
2.7 – 3.2 ps, “No load on Z”
96 – 108 ps, “0.1 fF load on Z”
Supporters
H2020 MCSA Research and Innovation Staff Exchange Programe
The Scientific and Technological Research Council of Turkey
3501-CareerProgram