1. Chapter 2 Power Electronic Devices

2. Bi-polar Transistor (BJT)
(C)
(E)
(B) I B C E V CE CB BE
(C)
(B)
(E) N P
(C)
(B)
(E)
Collector
Emitter
Base

3. Characteristics of Bi-polar TransistorV CE CB BE
Characteristics of Bi-polar Transistor I B1
Saturation Region I C V CE I B V BE
0.6 I B2
< B1
Linear Region
I = 0 B
Cut Off Region
Collector Characteristics
Base Characteristics

4. Closed switch Open switchR L V CC CE B I
B max B
= 0 V CE I C V CC R L
(1)
(2) V CC
Closed
switch
At point (1)
VCE is very small
At point (2)
IC is very small
Open
switch

5. Main Features of BJT Current controlled device
Base current must be present during the closing period
High base losses
Low current gain in the saturation region
Can operate at high frequencies

6. Field Effect Transistor (FET)

7. Main Features of FET
Voltage controlled device
Low gate losses

8. Thyristors (Four Layer Diode)

9. Thyristors [Silicon Controlled Rectifier (SCR)]
Anode (A)
Cathode (K)
Gate (G) I A V RB
Ig = 0
Ig = max
Ig > 0 Ih V TO V BO AK

11. Closing Conditions of SCR
Positive anode to cathode voltage (VAK)
Maximum triggering pulse is applied (Ig)
Anode (A)
Cathode (K)
Gate (G)
Closing angle is a

12. Opening Conditions of SCRA V RB
Anode current is below the holding value (Ih)
Ig = 0 Ih AK
Opening angle is b

14. Ratings of Power Electronic Devices
Steady State Circuit ratings:
The current and voltage of the circuit should always be less than the device ratings.

15. Ratings of Power Electronic Devices
Junction temperature: Losses inside solid-state devices are due to impurities of their material as well as the operating conditions of their circuits.

16. Ratings of Power Electronic Devices
During the conduction period, the voltage drop across the solid-state device is about one volt. This voltage drop multiplied by the current inside the device produces losses.
When the device is in the blocking mode (open), a small amount of leakage current flows inside the device which also produces losses.
The gate circuits of the SCRs and FETs, and the base circuits of the transistors, produce losses due to their triggering signals.
Every time the solid state device is turned on or off, switching losses are produced. These losses are usually higher for faster devices, and for devices operating in high frequency modes.

19. Ratings of Power Electronic Devices
Surge current: It is the absolute maximum of the non-repetitive impulse current

20. Ratings of Power Electronic Devices
Switching time:
Turn-on time is the interval between applying the triggering signal and the turn-on of the device.
The turn-off time is the interval from the on- state to the off-state.
The larger the switching time the smaller is the operating frequency of the circuit.

21. Ratings of Power Electronic Devices
Critical rate of rise of current (or maximum di/dt): A solid-state device can be damaged if the di/dt of the circuit exceeds the maximum allowable value of the device. di/dt damage can occur even if the current is below the surge limit of the device. To protect the device from this damage, a snubbing circuit for di/dt must be used.

22. Ratings of Power Electronic Devices
Critical rate of rise of voltage (or maximum dv/dt): When dv/dt across a device exceeds its allowable limit, the device is forced to close. This is a form of false triggering. It may lead to excessive current or excessive di/dt. To protect the device against excessive dv/dt, a snubbing circuit for dv/dt must be used.

23. di/dt and dv/dt Protection
Load V L s R C + -
© M. A. El-Sharkawi, University of Washington

24. © M. A. El-Sharkawi, University of Washington
Closing Switch R C s s + - I L 2 s
Load V I 1
Load impedance
© M. A. El-Sharkawi, University of Washington

25. Closing Switch: Analysis of I1
Load V L s I 1
LL, RL, CL
© M. A. El-Sharkawi, University of Washington

26. Closing Switch: Analysis of I1
Load V L s I 1
© M. A. El-Sharkawi, University of Washington

27. © M. A. El-Sharkawi, University of Washington
Snubbing Circuit: Ls
Worst Scenario for Maximum di/dt: When the load capacitor is not charged at t=0
© M. A. El-Sharkawi, University of Washington

28. Closing Switch: Analysis of I2
The fully charged cap discharges after the switch is closed R C s s + - I 2 L s V
Load
© M. A. El-Sharkawi, University of Washington

29. Closing Switch: Analysis of I2R C s s + -
At t = 0 I 2 L s V
Load
© M. A. El-Sharkawi, University of Washington

30. © M. A. El-Sharkawi, University of Washington
Opened Switch R C s s + - L s
Load V I 3
Load impedance
© M. A. El-Sharkawi, University of Washington

31. © M. A. El-Sharkawi, University of Washington
Opened Switch R C s s + - L s V I
Load 3
© M. A. El-Sharkawi, University of Washington

32. © M. A. El-Sharkawi, University of Washington
Opened Switch
Assume the caps are initially discharged R C s s + - L s V I
Load 3
© M. A. El-Sharkawi, University of Washington

33. Selection of the Snubbing Circuit Parameters
Step 1: Compute snubbing inductance
Step 2: Compute snubbing Resistance
Step 3: Compute snubbing Capacitance
© M. A. El-Sharkawi, University of Washington