1. Subject Name: Microprocessors Subject Code:10EC46 Department: Electronics and Communication Date:

2. Engineered for Tomorrow
UNIT:7
SYSTEM BUS STRUCTURE

3. Contents
Basic 8086 configurations.
Minimum mode
Maximum mode
Bus Interface
Peripheral component interconnect(PCI)
Parallel printer interface(LPT)
Universal serial bus(USB)

4. BASIC 8086 CONFIGURATION
In order to adapt to as many situations as possible in the 8086 have been given two modes of operation,
the minimum mode.
the maximum mode.

5. Minimum Mode Operation similar to 8085 (8 bit processor)
MN/MX* pin connected to +5 V
8-bit peripherals can be used with 8088/8086
Fig: Block Diagram of Minimum mode operation

6. Maximum Mode
Enhanced Operation used whenever a coprocessor is used with 8088/8086
MN/MX* pin connected to GND
8288 Bus Controller required to generate extra signals

7. Bus interface

8. PCI Bus
Work began in 1990
Intel began work on a new bus for their Pentium systems
Processor independent
To support higher bandwidth requirements of window-based systems
Original version (1.0) developed by Intel in 1990
Version 2 in 1993
Version 2.1 in 1995
Version 2.2 introduced power management for mobile systems

9. PCI bus(cont..) Transaction Control Signals Cycle Frame (FRAME#)
Indicates start of a bus transaction
Also indicates the length of the bus transaction cycle
Initiator Ready (IRDY#)
During Write transaction:
Indicates the initiator has placed data on AD lines
During Read transaction:
Indicates the initiator is ready to accept data
Target Ready (TRDY#)
Complements IRDY# signal
IRDY# and TRDY# together implement handshake to transfer data

10. PCI bus(cont..) Transaction Control Signals Stop Transaction (STOP#)
Target asserts this to tell initiator that it wants to terminate the current transaction
Initialization Device Select (IDSEL)
Used as a chip select for configuration read and write transactions
Device Select (DEVSEL#)
Selected target asserts this to tell the initiator that it is present
Bus Lock (LOCK#)
Imitator uses this to lock the target to execute atomic transactions

11. PCI bus(cont..) Bus Arbitration Signals
Uses centralized bus arbitration with independent request and grant lines
Bus Request (REQ#)
A device asserts when it needs the bus
Bus Grant (GNT#)
Bus arbiter asserts this signal to indicate allocation of the bus
Bus arbitration can overlap execution of another transaction
Improves PCI performance

12. PCI bus(cont..) Error Reporting Signals Parity Error (PERR#)
All devices are expected to report this error
Exceptions exist
E.g. when transmitting video frames
System Error (SERR#)
Any PCI device can generate this signal
To indicate address and other errors
Typically connected to NMI (non-maskable interrupt)

13. PCI bus(cont..) 64-bit Extension Signals
Address/Data Lines (AD[ ])
Extension to 64 bits
Command bus (C/BE#[4 - 7])
Extended by 4 lines to handle 8 bytes
Request 64-Bit Transfer (REQ64#)
Indicates to target that initiator likes 64-bit transfers
Acknowledge 64-Bit Transfer (ACK64#)
Target indicates that it is capable of 64-bit transfers
Parity Bit for Upper Data (PAR64)
Even parity for upper 32 AD bits and four command lines

14. PCI bus(cont..) Interrupt Request Lines Four interrupt lines
INTA#, INTB#, INTC#, INTD#
Not shared
Additional signals
To support snoopy cache protocol
IEEE boundary scan signals
Allows in-circuit testing of PCI devices
M66En signal to indicate bus frequency
Low: 33 MHz
High: 66 MHz

15. PCI bus(cont..)
A command value is placed on C/BE lines during the address phase
I/O operations
I/O Read and I/O Write
Memory operations
Standard memory operations
Memory Read and Memory Write
Bulk memory operations
Memory Read Line
Memory Read Multiple
Memory Write-and-Invalidate

16. PCI Operations
PCI read

17. PCI WRITE

18. PCI Bus Arbitration Uses centralized arbitration
Independent grant and request lines
REQ# and GNT# lines for each device
Does not specify a particular policy
Mandates the use of a fair policy
Two delay components
Arbitration overlaps with another transaction execution

19. PCI Bus Hierarchies Allows bus hierarchies
Built using PCI-to-PCI bridges
Need two bus arbiters
One for the primary bus
One for the secondary bus
Example: Intel PCI-to-PCI bridge
Secondary bus can connect up to 4 devices
One internal arbiter available
Can be used on the secondary side
Need external arbiter for the primary side

20. PCI Bus Hierarchies(Cont…)

21. PCI Delays 66 MHz implementations pose serious design challenges
All delays are cut in half compared to 33 MHz clock

22. THE PARALLEL PRINTER INTERFACE (LPT)
The parallel printer interface (LPT) is located on the rear of the PC.
LPT stands for line printer.
The printer interface gives the user access to eight lines that can be programmed to receive or send parallel data.
The parallel port (LPT1) is normally at I/O addresses 378H, 379H, & 37AH from DOS or by using a driver in Windows
The secondary (LPT2) port, if present, is located at 278H, 279H, & 27AH.
The connectors are shown in Figure 15–13

23. The connectors used for the parallel port.
the Centronics interface on the parallel port uses two connectors
a 25-pin D-type on the back of the PC
a 36-pin Centronics on the back of the printer .
The parallel port can work as both a receiver and a transmitter at its data pins (D0–D7).
allows other devices such as CD-ROMs, to be connected to and used by the PC through port
Anything that can receive and/or send data through an 8-bit interface can and often does connect to the parallel port (LPT1) of a PC.

24. Ports 378H, 379H, and 37AH as used by the parallel port.
the data port (378H)
the status register (379H)
an additional status port (37AH)
note that some of the status bits are true when logic 0

25. THE UNIVERSAL SERIAL BUS
The universal serial bus (USB) has solved a problem with the PC system.
Current PCI sound cards use internal PC power, which generates a lot of noise.
USB allows the sound card to have its own power supply, for high-fidelity sound with no 60 Hz hum
Other benefits are ease of connection and access to up to 127 different connections.
The interface is ideal for keyboards, sound cards, simple video-retrieval, and modems. Data transfer speeds are 480 Mbps for full-speed USB 2.0 operation.
11 Mbps for USB 1.1 compliant transfers
1.5 Mbps for slow-speed operation
Cable lengths are limited to five meters for the full-speed interface and three meters maximum for the low-speed interface.
Maximum power through the cables is rated at 100 mA, maximum current at 5.0 V.

26. The Connector two types of connectors are specified, both are in use
there are four pins on each connector, with signals indicated further.
the +5.0 V and ground can power devices connected to the bus
data signals are biphase signals
when +data are at 5.0 V, –data are at zero volts and vice versa

27. USB Data
Data signals are biphase signals generated using a circuit such as shown in Fig 15–16.
The line receiver is also shown.
A noise-suppression circuit available from Texas Instruments (SN75240) is placed on the transmission pair
Once the transceiver is in place, interfacing to the USB is complete.
Fig: The interface to the USB using a pair of CMOS buffers.

28. Fig NRZI encoding used with the USB.
USB uses NRZI (non-return to zero, inverted) encoding to transmit packet data
this method does not change signal level for the transmission of logic 1
signal level is inverted for each change to logic 0
Fig  NRZI encoding used with the USB.

29. USB data transmision(Cont..)
Actual data transmitted includes sync bits, a method called bit stuffing, because it lengthens the data stream.
If logic 1 is transmitted for more than 6 bits in a row, the bit stuffing technique adds an extra bit (logic 0) after six continuous 1s in a row.
Bit stuffing ensures the receiver can maintain synchronization for long strings of 1s and data are always transmitted with the least-significant bit first, followed by subsequent bit

30. a bit-stuffed serial data stream and the algorithm used to create it from raw digital serial data

31. USB Commands
To begin communication, sync byte 80H is transmitted first, followed by the packet identification byte (PID).
The PID contains 8 bits.
only the rightmost 4 bits contain the type of packet that follows, if any
The leftmost 4 bits of the PID are the ones complementing the rightmost 4 bits.

32. The types of packets and contents found on the USB.

33. The USB Bus Node
National Semiconductor produces a USB bus interface easy to interface to the processor.
Connect this device using non-DMA access:
connect the data bus to D0–D7
connect control inputs RD, WR, and CS and a 24 MHz fundamental crystal across XIn and XOut pins
The USB bus connection is located on the D– and D+ pins.
Figure 15–20 shows a USBN9604 USB node.

34. USBN9604 is a USB bus transceiver that can receive and transmit USB data
this provides an interface point to the USB bus for a minimal cost of about two dollars

35.   The USBN9604 interfaced to a microprocessor at I/O addresses 300H and 301H.

36. Thank you