1. on behalf of the AGH and UJ PANDA groups
Electronics status
J. Smyrski
on behalf of the AGH and UJ PANDA groups
Tests of the AGH front-end ASIC
News on the TRB v.3

2. Front-end architecture

3. ASIC – first prototype

4. The ASIC test-board v. 2. 1 ASIC (4 channels) Digital LVDS outputs
Buffered analog outputs
ATMega controller
for ASIC parameters
(gain, shaping)
Baseline and threshold
set with external voltage
source

5. Examples of output pulses
(Radioactive source: 55Fe)
tail due to saturation
in the shaper
HV: 1950 V
HV: 1800 V

6. Examples of output pulses
(Radioactive source: 90Sr)
tail due to saturation
in the shaper
HV: 1800 V
HV: 2000 V

7. TOT spectra with 55Fe TOT spectra Counts vs. HV HV= 1650 V 1750 V

8. TOT measurement with 55Fe

9. TOT measurement with 90Sr
(four
different
thresholds)
Drift time [ns]
TOT [ns]
Drift time [ns]
TOT [ns]

10. ASIC test board (v. 3.)
32-channel board (8 times 4-channel asic on board)
individual threshold control for each channel
two 2*17 pin 100 mils header input connector
LEMO test input: odd channels, even channels, all channels charge injection
individual base line setting for each asic
40 12-bit DACs on board (5 times 8-channel chip)
time over threshold digital LVDS outputs
buffered analog outputs:
common mode voltage = baseline voltage
pulse amplitude 0 – 1 V
positive pulse
ATMega controller for asic parameter and DAC setting
USB 2.0 access from PC
serial access from TRB
17 cm
13 cm

11. TRB v.3 – STT read out system status

12. Multi-Test AddOnn