1. ECE 3430 – Intro to Microcomputer Systems
ECE 3430 – Introduction to Microcomputer Systems University of Colorado at Colorado Springs
Lecture #14
Agenda Today
Illegal Opcode Interrupt
SWI, WAI, and STOP HC11 Instructions
Computer Operating Properly (COP) Watchdog
Clock Monitor
HC11 Free-Running Timer (TCNT)
Timer Overflow Interrupt
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

2. ECE 3430 – Intro to Microcomputer Systems
Interrupts
Illegal Opcode Trap - If the CPU is expecting an opcode and the control unit doesn’t recognize the machine code, an illegal opcode interrupt is thrown. - This IRQ is non-maskable or always on. - If this occurs, the CPU has lost control of the program and needs to be re-initialized. This can happen if a large noise spike enters the CPU or if the programmer modified
program memory directly without using the assembler. - It is good practice to reinitialize everything (STACK, etc…) or just reset the CPU. - We *should* always have the vector table setup for this: ORG $FFF8 ; initialize the illegal opcode trap vector table entry FDB IOT_ISR : IOT_ISR: SEI ; make sure no maskable interrupts occur LDS #$00FF ; re-initialize the stack LDAA #$00 ; perhaps re-initialize all registers
LDAB #$00
LDX #$ LDY #$ JMP MAIN ; we don’t need RTI because we re-init the stack pointer
; ‘MAIN’ is a label for the first line of the main loop
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

3. ECE 3430 – Intro to Microcomputer Systems
Interrupts
Interrupt Overhead - Interrupts take 12 clock cycles to initialize and get ready to execute the ISR. RTI takes clock cycles to return the program to normal operation. - The overhead should be measured to determine if an IRQ should be used. If the interrupts
occur too close together, some may be lost! - If something tries to interrupt every 20 clock cycles, every other interrupt will be “lost”.
The HC11 cannot acknowledge interrupts this quickly.
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

4. ECE 3430 – Intro to Microcomputer Systems
Interrupts
Software Interrupt Instruction (SWI) - This is an instruction that we can use to force an interrupt (SWI). This is an example of a
software-generated interrupt. - This is a non-maskable interrupt (makes sense since we explicitly call it—if we wanted to
mask it, we wouldn’t call it in the first place). - Used for debugging of code (software debuggers would use it to set breakpoints).
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

5. ECE 3430 – Intro to Microcomputer Systems
Interrupts
Example) Insert a breakpoint in the main loop that will stop the normal execution
of the program until PA0 is a logic 0. Perhaps an active-low pushbutton
is interfaced to PA0. This push would be the “resume” button.
ORG $FFF6 ; initialize the SWI vector table entry FDB SWI_ISR
ORG $FFFE ; initialize reset vector table entry FDB $E ORG $E000 ; begin code at top of EEPROM SEI ; disable maskable interrupts LDS #$FF ; initialize stack pointer
MAIN: … ; do something
SWI ; at this point, stop program
… ; do something
DONE: BRA DONE ; done *
* SWI service routine
SWI_ISR: LDAA PORTA ; now wait until a ‘0’ is present on PA0
ANDA #% BNE SWI_IRQ
RTI
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

6. ECE 3430 – Intro to Microcomputer Systems
Interrupts
Semi-Low Power Mode (WAI)
- When not using the CPU, we might like to stop operation to save power. Maybe we need
to synchronize software execution with the occurrence of an interrupt. - “Wait for Interrupt” (WAI) is an instruction that can do this Puts the microcontroller in a semi-low power mode (no opcodes read but keeps
clock oscillator running).
- The programming model registers/accumulators are stored to the stack (just like
when an interrupt occurs). This is done in anticipation of the interrupt that will occur
to satisfy the wait.
- While waiting, the CPU is issuing “dummy reads” to RAM—when the clock oscillator
is running, the CPU has to do *something*. - The CPU only resumes when a non-maskable interrupt, XIRQ, or RESET occurs.
- When the interrupt occurs, the CPU fetches the ISR vector and dives right into the
ISR (lower latency than normal since the WAI pushed the programming model ahead
of time).
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

7. ECE 3430 – Intro to Microcomputer Systems
Interrupts
Low power mode (STOP) - True low power mode can be accomplished using the STOP instruction. - This disables all clocks if the S-bit in the CCR is 0: S=1, STOP disabled, instruction is ignored (interpreted as NOP) S=0, STOP enabled - Since the clocks are stopped, the CPU does absolutely nothing and consumes very little
power.
- To get out of a STOP condition one of the following must occur (other interrupts are
ignored): IRQ (I-bit must be clear in CCR to resume from STOP) XIRQ (if X-bit is set in CCR, ISR is skipped and execution cont. after STOP)
RESET
- NOTE: If you try this in the lab, place a NOP instruction prior to the STOP (counters a
flaw in some HC11 mask sets [but likely all these faulty HC11s are long gone now]): …
NOP
STOP
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

8. ECE 3430 – Intro to Microcomputer Systems
Resets
Computer Operating Properly (COP) Watchdog Timer Reset - An independent free-running counter that will reset the CPU if it ever overflows
(internal reset). Theory - Under normal operation, code is written to clear the counter periodically.
- If software stops running for some reason, the counter will not be reset by the program and will overflow. This causes a RESET and the program will begin executing at the beginning.
- This provides auto-recovery from disaster situations (a requirement for
space craft for example). - To enable/disable the COP timer, we alter the ‘NOCOP’ bit in the ‘CONFIG’ register. NOCOP = 0, enabled (RESET condition) NOCOP = 1, disabled - The time it takes for the COP counter to overflow is called the “Timeout Period”. This can be programmed to 4 different values using the CR1 and CR0 bits in the OPTION register. CR1 CR0 E/
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

9. ECE 3430 – Intro to Microcomputer Systems
Resets
Computer Operating Properly (COP) Watchdog Timer Reset Example) CR1=0 & CR0=1 with XTAL = 8 MHz. What is the COP Timer Overflow Period? E-clock = XTAL/4 = 2MHz 2MHz = Hz  = Hz (215) Tcop = 1/( Hz) = ms
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

10. ECE 3430 – Intro to Microcomputer Systems
Resets
Computer Operating Properly (COP) Watchdog Timer Reset To reset the COP timer (when enabled): ) write $55 to COPRST, followed by 2) write $AA to COPRST TIMER AUTO-RESETS To initialize the interrupt vector table for the COP reset, we insert the beginning address of our ISR just like all the others: ORG $FFFA ; initialize COP reset vector FDB $E ORG $FFFE ; initialize RESET vector FDB $E000
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

11. ECE 3430 – Intro to Microcomputer Systems
Resets
Clock Monitor Reset - An RC circuit is present in the HC The capacitor is charged up with the clock. - If the clock stops, the stored charge will decay and trip a RESET (internal reset) Roughly: Eclk < 10kHz, trips reset Eclk > 200kHz, prevents reset
Reset is tripped
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

12. ECE 3430 – Intro to Microcomputer Systems
Resets
Clock Monitor Reset - The CME bit in the OPTION register will enable/disable the clock monitor reset interrupt CME = 0, disabled (Reset state) CME = 1, enabled
Remember:  = RC Vout = Vin · e-(t/)
Volts (V)
Time (t)
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

13. ECE 3430 – Intro to Microcomputer Systems
Timers
Timers - We want separate timing circuitry that will run independent of our program. This ensures more precise timing. Our program run times can be unpredictable due to interrupts! For
example, a DELAY subroutine or loop may take longer to complete if it is interrupted by
an interrupt. - The HC11 (D3) provides a timer sub-system (on-chip peripheral devices):
1) 16-bit Main Timer (TCNT) 2) Input Capture (4 channels) 3) Output Compare (5 channels) 4) Real Time Interrupts 5) COP Timer System 6) Pulse Accumulator
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

14. Main Timer
Free Running Main Timer (TCNT) / Timer Overflow Interrupt - A 16-bit counter clocked by a version of E-clock. - Has pre-scalar to slow count down. - When overflow occurs ($FFFF  $0000), an interrupt can be triggered On RESET, the counter is cleared to $ This counter is READ ONLY. - When overflow occurs, the “Timer Overflow Flag” (TOF) is set. - The “TOF” bit is located in the TFLG2 register ($0025) TOF = 1, overflow has occurred, to clear flag write a ‘1’ to TOF TOF = 0, waiting for overflow - The interrupt “Timer Overflow IRQ” is triggered on overflow: Global Enable = I-bit in CCR Local Enable = TOI bit in the TMSK2 register
Interrupt when logic 0 
TOI
Pre-Scalar divide by 1, 4, 8, or 16
Main Timer (TCNT) 16-bit
 IRQ  
E-clock  
TOF
TCNT High
TCNT Low
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

15. Main Timer Free Running Main Timer (TCNT) / Timer Overflow Interrupt
- The “Timer Overflow Interrupt” (TOI) flag is located in the TMSK2 register ($0024). TOI = 1, Enabled TOI = 0, Disabled (Reset state) - The “Timer Pre-Scalars” (PR1, PR0) are also in the TMSK2 register ($0024). PR1 PR0 Pre-Scalar Overflow Period (Eclk = 2 MHz) ms ms ms ms NOTE: The Pre-Scalars can only be changed ONCE, within the first 64 E-clock cycles.
Interrupt when logic 0 
TOI
Pre-Scalar divide by 1, 4, 8, or 16
Main Timer (TCNT) 16-bit
 IRQ  
E-clock  
TOF
TCNT High
TCNT Low
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

16. ECE 3430 – Intro to Microcomputer Systems
Main Timer
Free Running Main Timer (TCNT) / Timer Overflow Interrupt - When the “Timer Overflow” interrupt occurs (when enabled), the TOF flag is set.
- It is the responsibility of the ISR to clear the TOF flag before leaving the ISR. If the ISR
fails to clear the flag, the interrupt will not go away—as soon as you execute RTI, the
ISR will enter again.
FLAG REGISTERS ARE DESIGNED TO ONLY ALLOW SOFTWARE TO CLEAR BITS IN THEM! ONLY HARDWARE CAN SET THE FLAGS!
To clear bits in flag registers, software writes a one to that bit location. Writing a zero has
no effect!
To clear the TOF flag in the ISR, we would do the following (don’t use logic masks):
LDAA #% ; TOF bit is the most-significant bit in TFLG2 register
STAA TFLG2
Examples of flag registers: TFLG1, TFLG2
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

17. ECE 3430 – Intro to Microcomputer Systems
Main Timer
Free Running Main Timer (TCNT) / Timer Overflow Interrupt
Example) Use TCNT to pulse PA4 every ms.
* [PR1,PR0] = [01] = 4 = ms
TMSK2 EQU $24
TFLG2 EQU $25
PORTA EQU $00 ORG $FFDE ; initialize “timer overflow” vector table entry FDB TCNT_ISR
ORG $FFFE ; initialize “reset” vector table entry FDB $E ORG $E000 SEI ; disable maskable interrupts during setup LDS #$00FF ; initialize stack pointer
LDAA #% ; clear the timer overflow flag by writing a ‘1’
STAA TFLG2
LDAA TMSK ; enable local interrupt enable (TOI) by writing a ‘1’
ORAA #% ; set bit 1 to 0 and bit 0 to 1 (pre-scaler)
ANDA #%
STAA TMSK2
CLI ; enable maskable interrupts
DONE: BRA DONE
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009

18. PA4 Main Timer How accurate would you expect this waveform to be?
Free Running Main Timer (TCNT) *
* ISR for timer overflow interrupt.
* Pulse PA4 (1 -> 0) and clear the TOF flag.
TCNT_ISR: LDAA PORTA ; sample port A
ORAA #% ; force PA4 high (in ACCA), leave other bits alone
STAA PORTA ; force PA4 high on port A
ANDA #% ; force PA4 low (in ACCA), leave other bits alone
STAA PORTA ; force PA4 low on port A
LDAA #% ; force TOF (bit 7) low by writing a ‘1’, ‘0’ doesn’t effect other bits
STAA TFLG2
RTI ; always call RTI to leave interrupt service routines
131.1ms
ISR
PA4
How accurate would you
expect this waveform to be?
Lecture #14
ECE 3430 – Intro to Microcomputer Systems
Fall 2009