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Lecture Adders Half adder.

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Presentation on theme: "Lecture Adders Half adder."— Presentation transcript:

1 Lecture Adders Half adder

2 Full Adder si is the modulo-2 sum of ci, xi, yi.

3 An n-bit Ripple Adder FA Xn-1 Yn-1 Sn-1 Cn-1 Cn X0 Y0 ……… C1 FA C0 S0
MSB LSB

4 Adder/subtractor - = add 2’s complement of the subtrahend
y xor 0 = y; y xor 1 = ~y s 1 n x c -bit adder y Add Sub control

5 Overflow v.s. Carry-out n-bit signed number: -2n-1 to 2n-1 -1
Detect overflow for signed number: Overflow = Cn-1 ⊕ Cn Overflow = Xn-1 Yn-1 ~Sn-1 (110) + ~Xn-1 ~Yn-1 Sn-1 (001) where X and Y represent the 2’s complement numbers, S = X+Y. (sign bits 0, 0 ≠ 1 ) 0111 1111 Carry-out: for unsigned number

6 Propagate and Generate ripple carry
ci+1 = xiyi + (xi+yi)ci = gi + pici A ripple-carry adder: critical path = 2n + 1 x 1 y g p s Stage 1 Stage 0 c 2

7 Problem: ripple carry adder is slow

8 Carry-lookahead adder
Motivation: If we didn't know the value of carry-in, what could we do? When would we always generate a carry? gi is true. gi = ai bi When would we propagate the carry? pi is true. pi = ai + bi ci+1 = (bi.ci)+(ai.ci) +(ai.bi) = (ai.bi) + (ai+ bi) .ci c2 = g1 + p1 . c1 c3 = g2 + p2 . c2 c4 is computed once inputs (a0-a3, b0 to b3, and c0) are valid.

9 Propagate and Generate Carry-Lookahead
c1 = g0 + p0c0 c2 = g1 + p1g0 + p1p0c0 3 gate delays x 1 y g p s c 2 D1 D2 D3

10 Hierarchical CLA: Build a 16-bit adder using a block of 4-bit CLA.
Instead of producing the a carry-out from the most significant bit of the block, each block produces the generate and propagate signal for the entire block. For block 0, looking into c4, if all the 4 propagate functions are 1, then the carry-in c0 is propagated through the entire block, hence P0 = p3.p2.p1.p0, the rest in c4 represents the cases when this block produces a carry-out with generates, thus G0 = g3 + p3.g2 + p3.p2.g1 + p3.p2.p1.g0 So, c4 = G0 + P0.c0 Block x 7 4 y 3 1 Second-level lookahead c s P G 15 12 8 16

11 Second Level Equation c4 = G0 + (P0.c0)
The same principle as in the first level is used in the second level. The result of the second level is computed as soon as its inputs are valid. c4 = G0 + (P0.c0) c8 = G1 + P1c4 = G1 + P1G0 + P1P0c0 c12 = G2 + (P2.G1) + (P2.P1.G0) +(P2.P1.P0.c0) c16 = G3 + (P3.G2) +(P3.P2.G1) + (P3.P2.P1.G0) +(P3.P2.P1.P0.c0) In block 0

12 A Multiplier Array and adder

13 Array of Adders for Unsigned Multiplication
4-bit example


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