1. High-Speed Serial Interface Test in Production
Assure Device Interoperability In Real-World Environments
Welcome to the world of GuideTech
Today we present – HIGH-SPEED SERIAL INTERFACE TEST IN PRODUCTION
Listen and learn how the new high-throughput GT4000 with advanced CTIA & Datacom analysis tools can help assure your device performance in real-world system environments

2. Targeting production test of high-speed serial interfaces
About GuideTech
Specializing in Precision Timing for Semiconductor Test and Scientific Lab Communities since 1988
Core Technologies
Continuous Time Interval Analyzer (CTIA)
Fast Datacom Analysis Software (DCA)
High Channel Count, Parallel Architecture
Over the past decade, digital CMOS reigned king and most test equipment focused on digital solutions.
During this time, GuideTech developed innovations in precision timing solutions based on our Continuous Time Interval Analyzer technology, serving both the semiconductor test and scientific lab communities.
Our proven advantages in throughput and repeatability make GuideTech the perfect solution for cost-effective production test of PLL and high-speed serial interface test, in just milliseconds.
Targeting production test of high-speed serial interfaces

3. US Master Clock at the US Naval Observatory
Sample Applications
Semiconductor Test
PLL & Spread Spectrum Clocks
Source Synchronous Bus
Embedded-Clock Serial I/O
Scientific Analysis
Jet Engine Rotation/Vibration
Atomic Clock Drift & Particle decay
GuideTech Keeps the Planet’s time!
ASE test floor
US Master Clock at the US Naval Observatory
Some examples of the applications we address include:
Semiconductor Test – where we have over a thousand systems installed at major OEMs, Nearly every Assy & Test company worldwide, [CLICK]
and major fabless firms including QualComm and nVidia,.. providing high-throughput, multi-site test of PLLs, source synchronous clocks, and jitter analysis.
Other tests well suited for CTIA technology are serial signals of asynchronous nature such as: Source Synchronous Buses found on graphics display controllers, and embedded-clock serial interface devices such as PCI Express and Serial-ATA.
[Click}….[CLICK]
In the scientific community, our TIAs are used by NIST, NASA, while the drift of atomic clocks are monitored by GuideTech’s unique continuous TIA products. GuideTech in fact keeps the world’s time.

4. 2 pairs of differential channels @ >800Mbps
The Need for Speed
PCs move to high-speed serial buses in 20051
80% - 2.5Gbps PCI-Express
100% - 1.5Gbps Serial-ATA
20% - Gigabit Ethernet
But test quality is not yet assured!
1 Morgan Stanley – Sep 22, 2003 Semiconductor Capital Equipment Industry Research
2 pairs of differential >800Mbps
16 < 200Mbps
Controller
Device
Controller
Device
PCI Express is a rapidly emerging standard for chip to chip interconnect that is set to displace PCI and AGP parallel bus standards.
In addition, many other high speed standards are emerging in the SerDes realm including XAUI, fibre channel, Serial ATA, USB2, as well as (DVI) used for flat panels.
As interface speeds increase into the mulit-gigabit realm, ATE companies are struggling to keep up with the demanding test requirements.
Morgan Stanley forecasts that 100% of all PC will support some form of high-speed serial interface by the end of But with a continuing lack of cost-effective solutions for production ATE, test quality assurance is not yet assured!

5. Embedded-clock Serial
ATE Performance Gap
1.2G - 3.2G
Embedded-clock Serial
(e.g. XAUI, SATA, FC
& PCI-Express)
Performance
DUT
1.6G
Source Synchronous
Flat Panel DVI Digital Video Interface
GuideTech has been
filling the gap
since 2001
400MHz
+/-150ps
Digital
Synchronous
ATE
High Speed
High Accuracy
High Throughput
Asynchronous test
<CLICK> To illustrate, device frequencies have been increasing at an accelerating rate over recent years
<CLICK> While the majority of available ATE performance tops out between MHz with limited ability to measure precise timing on asynchronous signals
<CLICK> So as cost-sensitive consumer devices such as cell phone incorporate higher performance PLLs and Spread Spectrum Clocks…
<CLICK> …and as Graphics controller chips convert from RGB to 1.6Gbps Source Synchronous buses…
<CLICK> …And as multi-gigabit serial interfaces such as PCI Express proliferate in PC and communication applications…
<CLICK> …ATE companies are racing to develop higher performance digital capabilities while struggling to find solutions that address the unique and challenging asynchronous, analog test requirements of these emerging high-speed serial interface technologies.
<CLICK>
Leveraging the power of CTIA continuous timestamping technology, GuideTech has been filling this gap since 2001 for high speed, high accuracy, high throughput, asynchronous test.
In addition to Continuous TIA timestamping technology, our Datacom Analysis software provides the highest throughput solution for pattern verification and jitter test of multi-gigabit serial interfaces in production.
Spread Spectrum PLL Clocks
To lower EMI emissions of cell phones & consumer devices
Year

6. A New Test Paradigm Scope CTIA & DCA Slow, Statistical Averaging
Gross test of Total Jitter & Eye
CTIA & DCA
Fast, Frequency Domain Analysis
Per-edge timing analysis
To illustrate the powerful advantages of our CTIA & DCA technologies, compare the traditional scope method of analyzing datacom jitter, [CLICK] which takes minutes to gather enough samples to statistically determine total jitter and data eye width with that of the Continuous Time Interval Analyzer, [CLICK] with its throughput optimized Datacom Analysis software that produces per-edge timing analysis for high throughput pattern verification and jitter analysis.
That crucial per-edge timing information improves test coverage and quality assurance while still maintaining an affordable cost of test.
In order to break the daunting test cost barrier we face today, the industry sorely needs this paradigm shift in test philosophy to insure the successful and rapid adoption of these emerging high-speed serial interfaces .

7. Continuous TIA Technology
Continuous Timestamps
Record edge timing & event count relative to (T0,E0)
Multiple measurement types derived from same data set
All measurement channels reference same (T0,E0)
Powerful Pulse Selection Arming
“Walk” measurements through data patterns
Skip pulses to measure specific pulses
Meas # Event # Timestamps
E T1 , T2
E T3 , T4
E T5 , T6
CTIA Local Memory
E E E E3
The secret to CTIA technology is the continuous timestamps.
Every measurement records both EDGE TIMESTAMP and the EVENT COUNT of the pulse being measured. [CLICK] All timestamps and event counts are correlated to a (T0,E0) reference at the beginning of each measurement set.
[CLICK] Event counts and timestamps for each measured edge are stored in local CTIA memory [CLICK] where a local DSP performs computations of selected measurements, such as pulse width or jitter, in real-time. [CLICK]
[CLICK] Notice that having access to Events and Timestamps all correlated to a single reference (t0,E0) enables multiple types of measurements to be computed from the same set of measured data. In this example, it is possible to compute pulse width, period, frequency modulation, jitter and data pattern verification from a single measurement data set.
[CLICK] In addition, as all measurement channels in a system reference the same (t0,E0) as well, it is possible to determine skew between channels with very high accuracy. [CLICK]
Important for repeatable test of serial interfaces, the CTIA’s powerful internal arming modes enable the user to select and control exactly where measurements are made in a serial data pattern.
T T1 T T T4 T T6
Meas # Event # Pulse Width
E T2 – T1
E T4 – T3
E T6 – T5
Real-Time DSP
PWE2

8. Non-Continuous TIA Drawbacks
Non-Continuous TIA based on simple Time Counter technology
Random, absolute measure of time intervals
No inherent reference to common (T0,E0)
Relies heavily on Statistical Analysis methods
Time interval # Time Interval #2
Requires physical Pattern Marker for highest accuracy
Pattern match adds test time to synchronize to patterns
Pattern match unreliable in presence of large jitter
Requires repeating SEARCH for one-shot measurements
PLL Lock Time
The continuous timestamping nature of our TIA technology is the advantage that enables high-throughput pattern validation and jitter test on these new high-speed serial interfaces.
Without correlation to a reference (T0,E0), non-continuous TIAs, which are primarily based on classic Time Counter technology, rely heavily upon statistical analysis of a large number of random, absolute time interval measurements to extrapolate various jitter components with numerous throughput and repeatability limitations.
[CLICK] Throughput being the most critical cost factor in high volume production test, these TIAs lack the throughput necessary to be viable in production because of their dependence on physical Pattern Marker circuits which synchronize measurements to unpredictable serial data streams.
[CLICK] Without time-correlation between measurements, even a simple PLL lock time test may require several search attempts and long test times which is also not viable in production.

9. CTIA Single-Shot Capability
Test PLL & Spread Spectrum Clocks in production
One-shot
Frequency
Modulation
Lock Time
Jitter
No arming
Picosecond accuracy
In milliseconds
8 in parallel
Up to 64 channels
This display of our CTIA, measuring a 25MHz Spread Spectrum Clock with a 30KHz modulation between 24.5 and 25.5MHz, illustrates the one-shot capture of Spread Spectrum Clock modulation over time. You can observe that we’ve captured 1000 measurements of frequency in a short timespan of 800us and can clearly determine that this Spread Spectrum Clock clock is operating properly.
The bottom graph illustrates the CTIA ability to capture PLL or Spread Spectrum Clock lock time in one-shot by continuously referencing all frequency measurements to time T0 when the Spread Spectrum Clock was shut down. In this example, the CTIA was able to capture a lock time of under 100us in a single-pass of frequency measurements.

10. CTIA Frequency Domain Analysis
CTIA time correlation enables plot of time interval error (TIE)
Dt Dt Dt Dt Dt Dt Dt 6
Auto Correlation Plot
Of Sinusoidal Jitter
TIE Dt (ps)
Time (us)
Unlike non-continuous TIA which rely heavily on unpredictable statistical analysis methods, Continuous TIA leverage the power of correlation between measurements to produce a powerful plot of Time Interval Error – also known as an Autocorrelation plot when analyzing signal jitter.
[CLICK] The CTIA Time Interval Error, or TIE function, records measured edge shifts relative to the ideal edge location.
[CLICK] In this example, the positive edge shifts on the first few pulses followed by the negative shifts on the subsequent pulses indicates a sinusoidal jitter present in this signal.
[CLICK] The time correlation of CTIA Time Interval Error measurements allow the application of FFT frequency domain analysis to easily and repeatedly identify and separate sinusoidal jitter components from the Random Jitter noise floor of an FFT spectral plot.
FFT of the TIE plot provides
the amplitude and frequency of sinusoidal jitter/modulation
AMPLITUDE
fjitter
FREQ

11. Functional Test of Non-deterministic Signals
ATE Digital Compare Method – Requires Match Mode to position strobes
Match
Non-continuous TIA – Requires Marker to locate desired bit location
Match
Pattern Marker
PM selects the next desired pulse to measure
One of the most basic, but challenging serial interface tests is simply trying to confirm device functionality by verifying an expected test pattern which is non-deterministic. [CLICK]
Due to the unpredictable output phase of the serial interface signals, digital ATE pin electronics and classic TIAs must use some form of synchronization circuitry to lock measurements onto the asynchronous serial data streams. [CLICK]
The drawback in both these cases of Pattern Match synchronization is twofold:
First, test times are longer depending on the time it takes to lock onto a data pattern
Secondly, reliability is uncertain when high jitter in a signal may make it difficult for pattern match circuitry to lock onto a signal [CLICK]
Our Continuous TIA easily and quickly reconstructs asynchronous serial data pattern by the use of a ‘Virtual Marker’ to control measurement location within a data pattern.
Continuous TIA – Reconstructs repeating signals with ‘Virtual Marker’
GT4000
T T T T3
E E E E7

12. CTIA “Virtual Marker” Per-edge jitter analysis
Edge isolation & reconstruction of non-deterministic bit patterns
Known Bit Pattern & UI
Selectable Bit Event Count
Correlated CTIA Timestamps (Tn,En)
More reliable than a physical pattern marker in high jitter signals
Reduces test times to milliseconds for…
Per-edge jitter analysis
Asynchronous pattern verification
[CLICK] Thus in hardware, the secret of CTIA technology is this “Virtual Marker” that owes its capabilities to the valuable information of the CTIA time-correlated Event Counts and Timestamps which are always referenced to the (T0, E0) at the beginning of every measurement set.
The benefits of CTIA “Virtual Marker” are: [CLICK]
Higher reliability in the presence of large signal jitter [CLICK] … [CLICK]
Faster test times for both Functional Pattern Verification & Per-edge Jitter analysis

13. Serial Interface Test in Production
Many test options
High-$peed ATE
BERT
Scope
Jitter Analyzers
Few cost-effective approaches
Loopback
On-chip DFT/BIST
Now that you know a little about the power of GuideTech’s CTIA technology, let’s go back to the problem of searching for a viable solution for testing of serial interfaces in production.
Although jitter test is not new to this industry, as there are many test options available, none of the traditional solutions have the speed or precision necessary for production test.
There are a few alternative approaches such as Loopback and on-chip DFT or BIST that are low-cost yet also have limited test coverage.
The fact remains, with these jitter-sensitive devices, the old days of ‘guaranteed by design’ or ‘no test’ is NOT an option anymore.
But ‘no test’ is not an option anymore…

14. Serial I/O Loopback Test
Benefits
Low-cost vs expensive ATE pin electronics
Addresses asynchronous issue with ATE
TXdiff
RXdiff
Drawbacks
Gross Functional Test only
Does not insure device interoperability in real-world system environments
We in the test industry have a reputation for being very creative in finding solutions to difficult problems which is why the semiconductor industry continues to impress the world with the speed of IC evolution over the past decades.
When we examine the innovative use of loopback techniques for serial interface testing we see that Loopback provides two valuable things:
A low cost solution
A means to perform at-speed functional pattern verification without the need for high-performance ATE pin electronics
[CLICK]
Loopback however, being only a gross functional test in a clean ATE test environment, fails to provide any level of confidence that a device will operate properly in its real-world system application

15. Assure Real-World Performance
BER helps insure real-world performance but is too slow for production
High-throughput jitter analysis can estimate BER in production
Near-end
Far-end
TX Jitter Analysis
Predicts far-end jitter degradation after TX signal is subjected to system connectors, switches and PCB traces
Traditionally, Bit Error Rate measurements were the key determination of device quality and a reasonable prediction of how a device would perform in its real-world system environment.
However, as Bit Error Rate Testers take minutes, hours, or even days to complete a measurement, BERT instruments are not viable production test solutions.
Years of correlation studies have proven that an accurate measure of jitter components will provide a reliable means of estimating Bit Error Rate in a fraction of the time of a BER tester.
Thus a fast jitter analysis instrument, such as the CTIA with its “Virtual Marker” and powerful Datacom Analysis software, can provide a fast means to measure jitter in a loopback data path thus increasing test coverage and quality assurance for high-speed serial interfaces.
TXdiff
RXdiff
CTIA measures TX jitter
in loopback path

16. Random Jitter Causes of Random Jitter
Thermal noise
Transistor current fluctuation ‘shot’ noise
Flicker noise (1/f noise)
Random Jitter is a contributing factor to Bit Error Rate
BER
10-6
10-8
10-10
10-12 SJ
One of the most important components of jitter to be tested is Random Jitter, as it is a key parameter to estimate Bit Error Rate.
Some of the causes for Random jitter stem from internal device issues such as thermal noise. DJ
Eye
BER 10-12
QxRJ
Q = BER 10-12

17. RJ is important for fast BER estimation
Measuring Bit Error Rate on a BERT can take hours or days
Quickly determine Total Jitter for a BER of 10-12
Jitterp-p = ( Q x RJRMS ) + DJ
Q = BER 10-12
Due to the large Q multiplication factor, RJ measurements must not be contaminated by PJ and DDJ components
QxRJ
BER
10-12
Probability Density Functions (PDF) of jittering edge timing
As Bit Error Rate Testers can take hours or days to complete a measurement, determining Random Jitter in a few hundred millisecond is a true breakthrough in test paradigm when it comes to the serious challenges we face with serial interface testing.
However, a fast instrument is not useful if the Random Jitter measurements are not accurate and repeatable.
The Q-factor can erroneously exaggerate the Total Jitter result beyond the allowable device specification and thus inadvertently cause a good device to be determined as bad.
On the bottom of this slide we see how different jitter components, such as Periodic and Data-Dependent Jitter, can contaminate the measurement data and make it difficult to accurately and repeatedly determine the true gaussian Random Jitter in a signal.
This would lead to yield loss if too many ‘good’ devices fail because RJ results were erroneously large and then multiplied by 14 putting the Total Jitter result out of the device specification limits.
Gaussian RJ RJ contaminated by PJ RJ contaminated by DDJ

18. Data-Dependent Jitter is Important
Most PHY-layer I/O failures are DDJ-related
Causes of DDJ
Bandwidth limitations in signal path
Frequency dependent
Pattern dependent
Output driver faults
Duty cycle distortion
Rise/fall times
Packaging
Data-Dependent Jitter is one of the most difficult and time consuming measurements to make on many instruments due to the impact of instrument and test fixtures.
But DDJ is an extremely important jitter component to validate because many PHY-layer I/O failures are DDJ-related.

19. CTIA DataCom Jitter Analysis
GuideTech DCA Provides:
Data Pattern Verification
Random Jitter (RJ)
Data-Dependent Jitter (DDJ)
Periodic Jitter (PJ)
Total Jitter (TJ)
Bit Error Rate (BER)
Eye Width
At GuideTech, we have combined the power of CTIA ‘Virtual Marker’s continuous time-stamping technology with sophisticated Datacom Analysis software to provide the highest throughput serial pattern verification and jitter analysis solution available today.
[CLICK] With the availability of fast, accurate Continuous TIA technology and DCA software, adding test coverage and quality assurance becomes a reasonable investment in signal integrity test.
Continuous TIA technology enables
fast and accurate quality assurance

20. RJ contaminated by PJ & DDJ
CTIA RJ Immune to PJ
CTIA continuous timestamping enables isolation of the RJ noise floor by removal of PJ frequency components in the FFT spectrum and DDJ using virtual marker
Statistical (Curve fit) methods are prone to estimation errors depending on the PDF shape
0.1MHz MHz MHz
Jitter Amplitude (UI)
1UI
0.5UI
0.1UI
Remove Spread Spectrum Clock Modulation
Remove other periodic jitter
Remaining Noise Floor
(Random RMS Jitter)
PDF showing
RJ contaminated by PJ & DDJ
As I explained earlier, using the TIE or Time Interval Error function, the CTIA is able to create the jitter autocorrelation function.
Since all CTIA measurements are time correlated back to a unique time and event reference, an FFT of the Autocorrelation Plot results in a frequency spectrum that easily isolates PERIODIC JITTER COMPONENTS from the jitter noise floor and DDJ before computing RANDOM Jitter.
This frequency domain analysis method is the reason the CTIA Datacom Analysis produces Random Jitter results that are immune to effects of Periodic, Sinusoidal Jitter in signals.
Statistical or Curve Fit methods, on the contrary, are sensitive to PDF shape, making them prone to RJ estimation errors and not be very repeatable.

21. RJ Immunity to DDJ
CTIA continuous timestamps act as a ‘virtual’ marker
Isolate edges
Remove DDJ offset before performing FFT for RJ analysis T0
IDEAL Edge-6 location
Count
CTIA correlation of event count and timestamps to a common reference enables isolation of timing measurements on a per-edge basis.
This facilitates removal of DDJ shifts from the edge PDF histograms before performing frequency domain analysis to determine the Random and Periodic Jitter.
DDJ offset
1P N 2P N P N

22. CTIA vs. ‘double-delta’ method
CTIA measures edge shifts independently on each data bit
Produces highly repeatable DDJ results per-edge
Avoids inaccuracies of statistical double-delta methods* P1 N1 P2 N2 P3 N3 P4 N4 P5 N5 P6 N6
*Reference: Fibre Channel MJS document Section &
Inherent DDJ inaccuracies of double-delta method*
Non-Continuous TIA
Continuous TIA
The ability to isolate each edge also enables the CTIA produce highly repeatable DDJ results on a per-edge basis.
[CLICK]
In addition, the CTIA per-edge isolation method avoids the inaccuracies inherent in other worst-case double-delta statistical methods utilized by non-continuous TIA instruments

23. 10x Throughput with Picosecond DCA Correlation to Scope
DCA correlates to Agilent within picoseconds
DCA test time is less than 1 sec vs. 10 sec on scope (K28.5)
Results of DCA jitter analysis compare well with advanced oscilloscopes such as the Agilent DCA-J.
Here we show GT4000 Total Jitter results that are within a few picoseconds of the scope reading.
And Random Jitter, Deterministic Jitter and Periodic Jitter are also all within a couple of picoseconds of the scope results.
But while the oscilloscope took over 10 seconds to analyze a 20-bit K28.5 test pattern, the GuideTech GT4000 performed the analysis in under 1 second.

24. DCA Fast Jitter Separation
Select DCA test time
Pattern length
PJ resolution
PJ ON/OFF
RJ precision
Test Time (sec)
PJ – ON (RJ, DDJ, PJ, TJ)
} PJ resolution
10s 5s 1s
250ms
} RJ precision
PJ – OFF (RJ, DDJ & TJ only)
Test PCI Express
in 1 second
(including pattern verify)
But what makes the GT4000’s CTIA & DCA technology an exciting breakthrough in this industry is the incredible throughput. [CLICK]
The GT4000 enables testing of PCI Express and other multi-gigabit serial interfaces in a matter of seconds or milliseconds.
Our DCA software allows the user to dial in a desired test time by varying parameters such as:
Pattern length
Periodic Jitter resolution
Inclusion or omission of PJ measurement [CLICK]
And RJ precision
Faster test times are possible by disabling PJ [CLICK]
A full RJ, DDJ, PJ, TJ jitter decomposition, including pattern verification on a 640-bit PCI Express Compliance Pattern, can be performed in less than 1 second. Now that’s fast! …And with those test times there really is no excuse to omit jitter test for cost reasons when the Return on Investment can be so high.
Pattern
Length
(bits)
K PCIe PRBS15
640 bit ,767 bits
Compliance Pattern

25. The Value of Jitter Test
Jitter test saves money
Test Escapes
Field Returns
RMA failure analysis
Lost Business
Yield Loss
Failing good devices
Time-to-Market Delays
Long characterization-to-production correlation time
Unprepared to debug unexpected process variation at final test
To highlight some of the savings that jitter test in production can provide, just look at your own costs relating to any of the following problems that occur when you ship untested devices that fail in the field.
Or imagine the time and cost lost when unexpected process variation occur and you have no ready analysis solution on your production ATE floor to help debug the issues.

26. CTIA Provides the Missing Pieces
Test Asynchronous signals
High Throughput “Virtual Marker”
Repeatable Jitter Analysis
64 Single-ended / 32 Differential
Introducing the
GT4000
Continuous TIA
Booth # 1420
GuideTech is committed to providing the missing pieces to help semiconductor manufacturers bring their high-speed serial interface devices to market on time and with high assurance that these devices will perform to specifications when operating in their real-world system environments.
[CLICK]
Introducing the new GuideTech GT4000 which offers :
The ability to test asynchronous serial signals
with very high throughput using its unique “virtual marker”
To provide highly repeatable jitter analysis results
On up to 64 single-ended or 32 differential channels
GUIDETECH – The Vital Component for the successful evolution of today’s high-speed ICs

27. High-Speed Serial Interface Test in Production
Assure Device Interoperability In Real-World Environments
2004