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Using Xilinx ChipScope Pro Tools

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1 Using Xilinx ChipScope Pro Tools
Jeremy Sandoval University of Washington May 28, 2013

2 Overview ChipScope Pro Software Information
Advantages of ChipScope Pro ChipScope Pro Cores Tutorial: Using the ILA (Integrated Logic Analyzer) Core to Debug a Design Step 1: Create and Implement the Project Step 2: Add ILA core to the design Step 3: Debug the Design Using ChipScope Pro Analyzer

3 What is ChipScope Pro? Software tool that if used early in the creation of a Xilinx FPGA project, greatly increases design and debug speed. With the ChipScope Pro tools, you can insert a logic analyzer, system analyzer, and virtual I/O low-profile software cores directly into design Allows you to view any internal signal or node The signals are captured and then brought out through the programming interface, leaving more pins for FPGA design

4 Why use ChipScope Pro? Complex FPGA designs can be very time consuming to debug ChipScope Pro tool can shorten the overall design time ChipScope Pro is integrated with Xilinx ISE software In-circuit debugging and verification of many nodes in design Find out what is happening on the chip at the die level

5 ChipScope Pro Cores Integrated Controller (ICON)
Used for communication between the embedded Integrated Logic analyzer (ILA), Integrated bus analyzer (IBA), and Virtual Input/Output (VIO) low-profile cores Integrated Logic Analyzer Used to monitor the internal signals of the FPGA design Both ILA and IBA require on-chip Block RAM Virtual Input/Output core Customizable core that can both monitor and drive internal FPGA signals in real time. Does not require on-chip Block RAM Agilent Trace Core 2 (ATC2) Customizable logic analyzer core, similar to the ILA core but does not use on-chip Block RAM

6 Using ChipScope Pro Once FPGA design is ready to test, place cores into the design: Attach internal nodes for viewing to the ChipScope Pro core Generating the cores by using the Core Generator, Core Inserter tool, or PlanAhead software Place and route the design in the Xilinx ISE software Download the bitstream to the device under test and analyze with the ChipScope Pro software

7 Tutorial: Using ChipScope Pro ILA Core to Debug a Design
Design Description: Push Button that controls a 2 bit state machine Sinewave selection Low, mid, and high frequency sine wave generators LEDs to display the current state Debouncing circuit Clean transition from high to low when button is pushed Dip Switches Enable or disable debouncing circuit

8 Step 1: Create and Implement the Project
Create a new VHDL project in the ISE Project Navigator Add the provided project files Add new ChipScope Definition and Connection File to top level Regenerate all cores Change hierarchy to soft Synthesize design Copy project and rename

9 Step 2: Add ILA Core to design
Double click .cdc file: opens the ChipScope Pro Inserter tool Click ICON then Next

10 Step 2 continued Set input trigger ports to 6
Set trigger widths and Match Types to settings in the tutorial file Move to next tab Capture Parameters to confirm

11 Step 2 continued Connect the ports to debug nets in next tab
Search for clk_bufg in pattern field, click make connections Repeat for the rest of trigger ports

12 Step 2 continued Verify connections, save and close core inserter tool

13 Step 2 continued Right-click Generate Programming File process and change the –g StartUpClk to the JTAG Clock under Startup Option then generate and download programming file to the board

14 Step 3: Debug Design using ChipScope Pro Analyzer
NOTE: Unable to complete these steps due to unsupported Xilinx platform The tutorial is posted on the Atlas Demo Board SharePoint page Summary of this step: ChipScope Pro Analyzer tool to view each sinewave (low, mid, and high frequency) plots, they look correct Error is in the selection circuit logic, when a button is pressed there is a glitch in the waveform (not a clean transition from different frequencies) Using the Analyzer, push the button and view the logic waveform to find out that the debouncing circuit was not enabled

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