1. Digital Integrated Circuits A Design Perspective
EE141
Digital Integrated Circuits A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolić
Timing Issues
January 2003

2. Synchronous Timing

3. Clock Uncertainties
Sources of clock uncertainty

4. Clock Nonidealities Clock skew Clock jitter
Spatial variation in temporally equivalent clock edges; deterministic + random, tSK
Clock jitter
Temporal variations in consecutive edges of the clock signal; modulation + random noise
Cycle-to-cycle (short-term) tJS
Long term tJL
Variation of the pulse width
Important for level sensitive clocking

5. Clock Skew and Jitter
Clk
tSK
Clk
tJS
Both skew and jitter affect the effective cycle time
Only skew affects the race margin

6. Positive and Negative Skew

7. Positive Skew
Launching edge arrives before the receiving edge

8. Negative Skew
Receiving edge arrives before the launching edge

10. ᵟ=-ve
ᵟ=-ve

12. Impact of Jitter
Absolute jitter tjitter
Cycle-to-cycle jitter Tjitter

13. worst

16. Clock Distribution H-tree Clock is distributed in a tree-like fashion
- Clock gating
- Clock conditioning
Balanced paths trees
- RC delay
H-tree
Clock conditioning is the ability to shut down parts of the clock network to reduce power dissipation.
clock gating to cut clock connection if a branch gets idle, saves clock power.
Clock is distributed in a tree-like fashion

17. More realistic H-tree
[Restle98]

18. The Grid System No rc-matching Large power
(excess interconnect)
The Grid System
-Grids are typically used in the final stage of clock network to distribute the clock to the clocking element loads.
-Delay from the final driver
to each load is not matched (fundamental difference with RC matched CDN)
-Allows late design changes, since CLK is easily accessible on die.
-Large power dissipation since it has lot of unncessary interconnect.

19. Example: DEC Alpha 21164 (width of final driver inverter)
(single phase clock on dynamic logic)
(width of final driver inverter)

21. EE141
21264 Clocking
Clock hierarchy

22. EV6 (Alpha 21264) Clocking 600 MHz – 0.35 micron CMOS trise = 0.35ns
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EV6 (Alpha 21264) Clocking
600 MHz – 0.35 micron CMOS
trise = 0.35ns
tskew = 50ps
tcycle= 1.67ns
Global clock waveform
2 Phase, with multiple conditional buffered clocks
2.8 nF clock load
40 cm final driver width
Local clocks can be gated “off” to save power
Reduced load/skew
Reduced thermal issues
Multiple clocks complicate race checking

23. Self-timed and Asynchronous Design
Functions of clock in synchronous design
1) Acts as completion signal
2) Ensures the correct ordering of events
Truly asynchronous design
1) Completion is ensured by careful timing analysis
2) Ordering of events is implicit in logic
Self-timed design
1) Completion ensured by completion signal
2) Ordering imposed by handshaking protocol

26. Latch-based clocking
- Latch based design in which combinational logic is separated by transparent latches (vicver)
- If a logic block finishes before the clock period, it has to idle till the next input is
latched in on the next system clock edge.
- The use of a latch based methodology (as illustrated in Figure 10.26) enables more flexible timing, allowing one stage to pass slack to or steal time from following stages. This flexibility, allows an overall performance increase.

27. Latch-based clocking For
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Latch-based clocking
--However, there is an important performance related difference. In a latch based system, since the logic is separated by level sensitive latches, it possible for a logic block to utilize time that is left over from the previous logic block and this is referred to as slack borrowing.
--This approach requires no explicit design changes, as the passing of slack from one block to the next is automatic. The key advantage of slack borrowing is that it allows logic between cycle boundaries to use more than one clock cycle while satisfying the cycle time constraint.
--Stated in another way, if the sequential system works at a particular clock rate and the total logic delay for a complete cycle is larger than the clock period, then unused time or slack has been implicitly borrowed from preceding stages.
--This implies that the clock rate can be higher than the worst case critical path!
For

28. Slack borrowing

29. Minimum clock period required is 125 ns

30. Refer: Bernstein[98] for slack borrowing
Minimum clock period required is 100 ns
Refer: Bernstein[98] for
slack borrowing

31. Synchronous Pipelined Datapath
Solution: Asynchronous design

32. Self-Timed Pipelined Datapath
This approach assumes that each combinational
function has a means of indicating that it has completed a computation for a particular
piece of data.

33. Asynchronous-Synchronous Interface
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Asynchronous-Synchronous Interface
sample at regular intervals and check its value
if the sampling rate is high enough, no transitions will be missed (Nyquist criterion)
signal is sampled in the middle of a transition (key press)/undefined state (Crash)
circuit that implements decision making function (high/low state) is called synchronizer
an asynchronous signal must be resolved to be either in the high or low state before it is fed into the synchronous environment. A circuit that implements such a decision-making function is called a synchronizer.
a synchronizer needs some time to come to a decision/ waiting helps reduce failure rate
Consider a typical personal computer. All operations within the system are strictly
orchestrated by a central clock that provides a time reference. This reference determines
what happens within the computer system at any point in time. This synchronous com-
puter has to communicate with a human through the mouse or the keyboard, who has no
knowledge of this time reference and might decide to press a keyboard key at any point in
time. The way a synchronous system deals with such an asynchronous signal is to sample
or poll it at regular intervals and to check its value. If the sampling rate is high enough, no
transitions will be missed—this is known as the Nyquist criterion in the communication
community. However, it might happen that the signal is polled in the middle of a transi-
tion. The resulting value is neither low or high but undefined. At that point, it is not clear
if the key was pressed or not. Feeding the undefined signal into the computer could be the
source of all types of trouble, especially when it is routed to different functions or gates
that might interpret it differently. For instance, one function might decide that the key is
pushed and start a certain action, while another function might lean the other way and
issue a competing command. This results in a conflict and a potential crash. Therefore, the
undefined state must be resolved in one way or another before it is interpreted further. It
does not really matter what decision is made, as long as a unique result is available. For
instance, it is either decided that the key is not yet pressed, which will be corrected in the
next poll of the keyboard, or it is concluded that the key is already pressed.
Thus, an asynchronous signal must be resolved to be either in the high or low state
before it is fed into the synchronous environment. A circuit that implements such a deci-
sion-making function is called a synchronizer.

34. Synchronizers and Arbiters
Arbiter: Circuit to decide which of 2 events occurred first
Synchronizer: Arbiter with clock f as one of the inputs
Problem: Circuit HAS to make a decision in limited time - which decision is not important
Caveat: It is impossible to ensure correct operation
But, we can decrease the error probability at the expense of delay

35. A Simple Synchronizer metastability
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A Simple Synchronizer
metastability
To illustrate why waiting helps reduce the
failure rate of a synchronizer, consider a synchro-
nizer as shown in Figure This circuit is a
latch that is transparent during the low phase of
the clock and samples the input on the rising
edge of the clock CLK. However, since the sam-
pled signal is not synchronized to the clock sig-
nal, there is a finite probability that the set-up
time or hold time of the latch is violated (the probability is a strong function of the transi-
tion frequencies of the input and the clock). As a result, one the clock goes high, there is a
the chance that the output of the latch resides somewhere in the undefined transition zone.
The sampled signal eventually evolves into a legal 0 or 1 even in the latter case, as the
latch has only two stable states.
• Data sampled on rising edge of the clock
since the sampled signal is not synchronized to the clock signal, there is a finite probability that the set-up time or hold time of the latch is violated (the probability is a strong function of the transition frequencies of the input and the clock). As a result, when the clock goes high, there is a chance that the output of the latch resides somewhere in the undefined transition zone.

36. Arbiters Decides which of the two events has occurred first
(Two CPUs demanding same resource)
The output consists of two Ack(nowledge) signals that should be mutually exclusive. While Requests may occur concurrently, only one of the Acknowledges isallowed to go high.

37. PLL-Based Synchronization
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PLL-Based Synchronization
There are numerous digital applications that require the on-chip generation of a periodic
signal. Synchronous circuits need a global periodic clock reference to drive sequential ele-
ments. Current microprocessors and high performance digital circuits require clock fre-
quencies in the gigahertz range. Crystal oscillators generate accurate, low-jitter clocks
with a frequency range from 10’s of Megahertz to approximately 200MHz. To generate a
higher frequency required by digital circuits, a phase-locked loop (PLL) structure is typi-
cally used. A PLL takes an external low-frequency reference crystal frequency signal and
multiplies its frequency by a rational number N (see the left side of Figure 10.56).
To generate a higher frequency required by digital circuits, a phase-locked loop (PLL) structure is typically used. A PLL takes an external low-frequency reference crystal frequency signal and multiplies its frequency by a rational number N

38. PLL