1. Development of CMOS sensors adapted to the vertex detector requirements
M.Winter, on behalf of
IPHC (ex-IReS) Strasbourg
DAPNIA Saclay (Mimosa-8,-15, ADC)
LPSC Grenoble (ADC)
LPC Clermont (ADC)
Univ. Frankfurt (Mimosa-11)
Fast integrated signal processing architecture
Delayed signal processing architecture
room temperature
Exploration of fabrication processes
Thinning
EUDET project, STAR upgrade
LCWS March 2006, Bangalore, India

2. Specific aspects of the CMOS VD concept
ADC, sparsification
pixels
Overall design a priori very similar
to TESLA TDR concept (CCD):
Basic characteristics:
Main R&D effort
5 cylindrical layers
inner most double sided ?
R = 15 – 60 mm
surface ~ 3000 cm2
support
sensor thickness
~ 35 m
total number of pixels
~ 300 millions
Pmean ~≤ 25 W
(full detector;
1/20 duty cycle)
operated T ~ 20oC
Layer
Pitch
tr.o.
Nlad
Npix
Pinstdiss
Pmeandis L1
20 m
25 s 20
25M
< 100 W
< 5 W L2
25 m
50 s 26
65M
< 130 W
< 7 W L3
30 m
200 s 24
75M L4
35 m 32
70M
< 110 W
< 6 W L5
40 m 40
< 125 W
total
142
305M
< 565 W
<29 W
 concentrated on
achieving fast CMOS sensors
 signal processing
(sparsification) integrated/chip
LCWS March 2006, Bangalore, India
Marc Winter

3. Status of the main R&D directions
Fast read-out in L1/L2 with // processing of columns
Mimosa 8 (with Saclay)  characterized in test beam.
Mimosa 15 (M8 pixel in AMS 0.35 opto)  tested in lab.
Multi-memory architecture (FAPS) in L3-L5
Mimosa 12  tested in lab.
Radiation hardness (Ionising high TºC
Mimosa 11  characterized in test beam.
 irradiated with 10 keV X-Rays up to 1 MRad.
other on going activities
Fabrication process characterisation
ADC
Thinning
Mimostar-2  data taking in real experimental conditions (end ‘06)
CMOS sensor beam telescope (EUDET-FP6 project)
LCWS March 2006, Bangalore, India
Marc Winter

4. // read-out architecture

5. // read-out architecture: Mimosa 8
Test in lab: 55Fe results
Pixel noise ~ 15 e-
CDS ending each column
 Pixel-to-pixel dispersion ~ 8 e-
Test beam results (DESY, 5GeV e-)
Analog part (see F.Orsini, Vienna Nov. ‘05)
Charge  ~ 450 e-  thin epi layer
Typical noise  ~ e-
S/N (MPV) ~
Digital part
The discriminator works as expected:
efficiency / purity / multiplicity
Next: AMS 0.35 OPTO, rad. tol. pixel,
ADC, speed
- TSMC 0.25 m fab. process with ~ 7 m epitaxial layer
Pixel pitch: 25 m
3 sub matrices with 3 diode sizes
1.2 x 1.2 μm2
1.7 x 1.7 μm2
2.4 x 2.4 μm2
24 // columns of 128 pixels with 1 discriminator per column
8 analog outputs
Vth = 2.5mV
w/o source
with source
Vth = 5.5mV
LCWS March 2006, Bangalore, India
Marc Winter
w/o source
with source

6. M8 digital : Efficiency and fake rate
Temp. = +20oC; r.o. = 40 MHz
Fake Hit rate / pixel / event
Average hit multiplicity
(number of pixels in cluster)
S/N(seed) cut > 4
( discri. threshold =3.4 mV)
Fake rate ~ 10-3
First sensor with integrated
signal digitisation !
Architecture may be extended
for EUDET beam telescope
LCWS March 2006, Bangalore, India
Marc Winter

7. Mimosa 15: translation in AMS 0.35 opto
TSMC – 0.25 technology
< 7 μm epitaxial layer thickness: signal ~ 450 e-
while AMS-0.35 OPTO techno
~< 12 μm thickness: signal ~ e-
Translate Mimosa 8 in AMS-0.35 OPTO technology
First step: Mimosa 15 (fabricated in Summer 2005)
Pixel with integrated CDS design of Mimosa 8
2 diode sizes: 1.7 x 1.7 μm2 & 2.4 x 2.4 μm2
Lab. tests in December-January
LCWS March 2006, Bangalore, India
Marc Winter

8. Mimosa 15: tests with 55Fe source
2.4 x 2.4 μm2 diode:
Noise ~< 10 e- ENC
Charge to voltage conversion gain ~ 50 μV/e-
Gain & Noise very close to Mimosa 8 ready for full translation of Mimosa 8
But: less signal charge collected  adapt sensing diode size
Qseed ~ 10% of Qtot (instead of ~ 25%)
Q3x3 ~ 30% of Qtot (instead of ~ 70%)
Cluster seed
Mean ~ 8.3 e-
2.4 x 2.4 μm2
T = 20 oC
25 MHz
Calibration peak
Charge (electrons)
Noise (electrons)
LCWS March 2006, Bangalore, India
Marc Winter

9. Multi-memory architecture

10. Multi-memory architecture (1)
Mimosa 12 (MOSAIC-1)
Layers 3-5 (& layer 2 ?)
Prototype exploring various types & dimensions of memory cells
AMS-0.35 m techno
4 capacitors/pixel (35 m pitch)
6 sub-arrays with various MOS capa.: 50, 100, 200 fF
Aim for minimal size capacitors providing satisfactory precision, depending on pitch - i.e. layer - (~ 4.6 fF/m2)
Minimal size of capacitor: ~ 50 fF (see also CAP for BELLE)
Cap : 100 fF
Cap : 200 fF
Cap : 50 fF
AC : Poly - Poly
AC : Nwell - Poly
Clamping
LCWS March 2006, Bangalore, India
Marc Winter

11. Multi-memory architecture (2)
4 capacitors / pixel
Calibration peak with 55Fe
With sampling and read-out
With direct read-out
Write
Read
Read
tint ~ 230 μs
 ~ O(1 ms)
Standard pixel
Without sampling
50 fF
100 fF
200 fF
Storage duration
is critical
LCWS March 2006, Bangalore, India
Marc Winter

12. Radiation hardness

13. Radiation hardness (1) Mimosa 11: structures Mimosa 11: test beam
AMS 0.35 μm opto.
8 different sub-matrices
Standard
rad tol: thin oxide and guard ring
Minimize leakage current
Mimosa 11: test beam
DESY, 5 GeV e-
T = +40 oC ; 700 μs (2.5 MHz)
S/N (MPV) ~ 24
Eff = 99,9  0.05 % SF SB p+ p+ n+ p+
P-Well
N-Well
P-epi
Standard (A0 sub 2)
P+ poly
filling
Partially
P+ doped
Partially
P+ doped
P+ poly
filling SF SB p+ n+ p+ n+ p+
P-Well
N-Well
P-epi
Rad hard (A3 sub 1)
LCWS March 2006, Bangalore, India
Marc Winter

14. Mimosa 11 200 μs 10 keV X-ray Temperature -25 °C 10°C 40 °C 0kRad
(with S. Amar-Youcef, C. Müntz, J. Stroth. Frankfurt)
Temperature
-25 °C
10°C
40 °C
0kRad
Noise (e-)
Standard structure
200 μs
500kRad
Integration time (ms)
Rad hard structure
4-pixel cluster: 55Fe spectrum before (red) and after (green)
1 Mrad of +40°C (200 µs integ. time)
Standard structure
Rad hard structure
ADC counts
LCWS March 2006, Bangalore, India
Marc Winter

15. Other on-going activities

16. Other on-going activities
Fabrication process exploration
TSMC 0.25 μm:
Typical cluster charge for MIP ~ 450 e-  Epi. Layer ~ 6.5 μm
AMS 0.35 μm OPTO:
S/N ~ (MPV) det ~ % ; sp = m (20 m pitch)
Process performances assessed (M9, M11, M14, M15)  engineering run for fab. yield estimate
Epi. Layer ~ 12 μm (new option: “20 µm”)
Process expected to remain available for many years
Will be used for EUDET, STAR
ADC
LPC-Clermont: full flash ADC  proto. fab. in Autumn 2005
LPSC-Grenoble: semi-flash ADC  proto. subm. in Dec 2005
DAPNIA & IPHC: Succ. approx. 4 & 5 bits  proto. subm. in March & June 2006
IPHC: Wilkinson double ramp (5 bits)
Thinning (Mimosa-5)
TRACIT company:
Thinning at 50 μm successful (mech.)  electrical tests foreseen
On going tests to thin down to μm
LCWS March 2006, Bangalore, India
Marc Winter

17. MimoSTAR 2 Efficiency vs Temp S/N (MPV) vs Temp (DESY, 5 GeV e-)
AMS 0.35 μm OPTO. 30 μm pitch
2 matrices 64 x 128, JTAG architecture
Rad. hard structure (based on Mimosa 11)
To be mounted on ladders installed in STAR (2006)  assessment in real exptal conditions
Ionising radiation tolerant pixel validated at temperature up to + 40 oC
No active cooling needed at int. time ~< O(1 ms)
Prototype of a beam telescope demonstrator chip (EUDET)
Efficiency vs Temp
S/N (MPV) vs Temp
Test-beam results
(DESY, 5 GeV e-)
2 r.o. time (2 and 10 MHz)
 800 μs and 4 ms
LCWS March 2006, Bangalore, India
Marc Winter

18. Plans for 2006

19. 2006 overview Engineering Run in AMS 0.35 OPTO (end June 06)
5 different sensors  ILC, EUDET, STAR
Several ADC prototypes
 spin-offs: 1) fabrication yield assessment
2) < 50 µm thinning trials and yield assessment
3) explore 20 µm epitaxy performances
Other chip fabrications
Mimosa-21 (multi-memory pixel for outer layers)
 8 capacitors per pixel (60 fF, 120 µs int. time, 26 µm pitch), 1 kHz r.o. freq.
 several different memory types (current and voltage)
V.D.S.M. process exploration: AMS O.18 µm OPTO ?
Start sparsification studies
Thinning
Aim for 35 µm thickness
Try several suppliers (eventually with full custom substrate)
Power cycling
DESY
LCWS March 2006, Bangalore, India
Marc Winter

20. Engineering Run in AMS 0.35 OPTO
Submission end June ‘06
Motivated by MIMOSTAR-3L :
200 kpixels, 30 µm pitch, tr.o. = 2 ms, 2 cm2
Other chips:
MIMOTEL: 0.8x0.8 cm2, rad.tol., 800 μs (EUDET)
MIMOSA-8+: fast read out architecture (EUDET, ILC)
MIMOSA-15+: Noise reduction, etc. (EUDET, ILC)
IMAGER: resolution ~1 μm (EUDET)
ADCs: flash, 1/2-flash, succ. app., ... (EUDET, ILC)
Epitaxy thickness «14» and «20» µm
Up to six 8 inch wafers, made of ~ 50 reticles each
Back from foundry in September ‘06
MIMO*3L
(640 x 320)
M-20
Mimosa 8+
(128 x32)
M-16
Imager
(512 x 512)
M-18
MIMOTEL
(256 x 256)
M-17
Mimosa 15+
(200 x400)
M-19
LCWS March 2006, Bangalore, India
Marc Winter

21. Summary Fast col. // architecture for inner most layers
Full chain up to discrimination validated on test beam
Next step (June ’06): translation in AMS 0.35 OPTO with rad. tol. pixel at Troom
In parallel: development of various 4-5 bits ADCs
Multi-memory pixels for outer layers
Sensors with 4 capa./pixel (35 µm pitch) characterised  ≥~ 50 fF mandatory (?)
New prototype in Autumn ’06: 8 capa./pixel (60fF, 120 µs integ. time), 26 µm pitch, current vs voltage memories
Fabrication process investigations
AMS 0.35 OPTO assessed (likely to remain available for several years)
estimate yield and study ~≤ 20 µm epitaxy option (engineering run in June ’06)
Study VDSM technology by end ’06 (e.g. AMS 0.18 OPTO)
Assessment of sensor operation in STAR (4 MIMO*-2 on ladders) by end ’06
Thinning: 50 µm thickness seems ~ OK (yield ?) try µm
LCWS March 2006, Bangalore, India
Marc Winter

22. Research team
IPHC: J. Baudot, A. Besson, G. Claus, C. Colledani, (G. Deptuch), M. Deveaux, A. Dorokhov,
W. Dulinski, M. Goffe, D. Grandjean, F. Guilloux, S. Heini, A. Himmi, Ch. Hu, K. Jaaskelainen,
M. Pellicioli, O. Robert, A. Shabetai, M. Szelezniak, I. Valin, M. Winter
DAPNIA: M. Besançon, Y. Degerli, E. Delagnes, N. Fourches, Y. Li, P. Lutz, F. Orsini
LPSC: D.Dzahini, M.Dahoumane, H.Ghazlane, J.Y.Hostachy, E.Lagorio, O.Rossetto, D.Tourres
LPCC: B.Bohner, R.Cornat, P.Gay, J.Lecoq, L.Royer
(Univ. Frankfurt: S. Amar-Youcef)
LCWS March 2006, Bangalore, India
Marc Winter

23. Mimosa 11 200 μs 10 keV X-ray Temperature -25 °C 10°C 40 °C 0kRad
(with S. Amar-Youcef, C. Müntz, J. Stroth. Frankfurt)
Temperature
-25 °C
10°C
40 °C
0kRad
20kRad
Standard structure
200 μs
500kRad
Rad hard structure
Noise (e-)
1000kRad
Integration time (ms)
LCWS March 2006, Bangalore, India
Marc Winter

24. M8 digital : Hit multiplicity
LCWS March 2006, Bangalore, India
Marc Winter

25. Multi-memory architecture (1)
Diode « self-bias »
Couplage AC 50fF
Ampli. Nmos G~10
4 capacités de stockage
Ampli. Source Follower
Cap : 200 fF
Cap : 100 fF
Diode « self-bias »
Couplage AC 50fF
Ampli. Nmos G~10
2 capacités de stockage « clamping » (CDS intégré)
Ampli. Source Follower
Cap : 50 fF
Diode « self-bias »
Couplage AC 50fF
Poly-Poly
Nwell - Poly
Ampli. Pmos G~7
4 capacités de stockage
( Cap =200 fF)
Ampli. Source Follower
AC : Poly - Poly
AC : Nwell - Poly
Clamping
LCWS March 2006, Bangalore, India
Marc Winter