1. Digital readout architecture for Velopix
Tuomas Poikela
University of Turku
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2. Outline Digital architecture Simulations
From pixel to super pixel, super pixel geometry
Packet format
On-chip clustering of hits
Some thoughts on periphery
Simulations
Data rates with different clustering solutions
Single column synthesizabe Verilog module, no periphery
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3. From pixel level to super pixel level
Motivation:
Hits typically come in clusters (Medipix testbeam, Gauss/Boole simulation data)
Without clustering, overall data rate produced by 6 hits per bunch crossing at 40 MHz and a cluster size of 3 is 23 Gbit/s (assuming 12b bunch id, 4b ToT, 16b address)
55 um x 55 um geometry of a pixel restricts the area available for processing logic in the pixel which is needed to reduce the data rate
All pixels in a super pixel can share this logic if proper buffering , resource arbitration and processing speed are used
Simultaneous hits from different pixels can share data fields in a packet: global address and bunch id can be shared
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4. Readout architecture
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5. Proposed floorplan of the active area
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6. Super pixel dimensions
4 x 4 pixel solution appears to be promising based on simulations
Optimal solution heavily depends on size and form of the clusters => Not a good solution for cluster size of one, 20b per pixel address
For cluster size of two gives 10b/12b per pixel address (vs. 16b without super pixel)
For cluster size of three 6.66b/8b/9.33b per pixel address
As an extreme case, cluster size of 16 reduces the address size to 2b per pixel
Non 2^N solutions are non-uniform and more complex than 2^N solutions to implement in hardware
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7. Super pixel dimensions tradeoffs
Advantages:
Readout logic, time stamp, address can be shared between pixels
Larger size decreases the chance of distributing a cluster between several super pixels => less data
Larger size increases the area available for common logic blocks
All buses can be shared between pixels (one bus per several single pixel columns)
Disadvantages:
Larger size increases the complexity of wiring the logic blocks together (wide multiplexers mainly)
Larger size requires faster processing because pixels are logically tied together => increased hit frequency in super pixel vs. pixel
Larger size breaks the pixel level uniformity => increases mismatch in analog front-end
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8. Super pixel functionality
Contains 16 pixels ( 4 x 4 )
Buffering implemented on cluster level
After 2 clusters (regardless of the size, 1-16 hits) a super pixel is dead until a cluster is transferred into 2nd stage buffer.
Configurable digital threshold: Clusters with more than N hits are discarded without writing them into buffers.
Threshold doesn’t take into account clusters split between several super pixels.
Merging of clusters can also be turned off
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9. Velopix Packet format
Only 6 address bit are needed on a column level. A 6b column address is
added to packets in the periphery.
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10. Address encoding with row header
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11. Merging clusters between super pixels
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12. Super pixel floorplan 140 um is an indicative number and not a fixed
design parameter!
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13. Super pixel group
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14. Columns + periphery X 4 Most of the buffering is in super pixels,
periphery only passes packets forward.
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15. Simulations specifications
Used hit coordinates from ntuples in ROOT files (from Gauss/Boole simulations), U-shaped module
Used Sensor 12, chip 4, all events (4 slots per event)
On the average 15 pixels hit per bunch crossing
Active area clocked at 40 MHz, DUT is a clock cycle accurate, synthesizable Verilog module
Used a poisson distribution with a mean of 7 (clock cycles) for ToT values
Effect of actual ToT from Gauss/Boole values still needs to modeled and observed
Efficiency: number of correct packets sampled from the column / number of packets sampled from input discriminator signals
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16. Hit distribution, sensor 12, chip 4
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17. Data rates from algorithmic simulations (no specific architecture)
Without address encoding from row header using fixed 16-bit hit map: 16.7 Gbps
Address encoding with row header (no merging of clusters): 14.6 Gbps
Address encoding with row header and merging clusters vertically in columns (previously shown): Gbps
Address encoding with row header and merging clusters vertically in columns and horizontically between columns: Gbps
1st option is the simplest in hardware, 4th is the most complex.
3rd was chosen
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18. Efficiency in columns vs. buffering size
Column number
Efficiency (only missing packets)*
Efficiency (correct packets)
FIFO buffer size, # words, header/data
99.45 %
98.83 %
4/10
98.84 %
8/16 32
99.27 %
98.50 %
6/12
99.31 %
98.61 %
98.62 %
10/20
99.24 %
98.57 %
12/24
*incorrect ToT values/missing shared information
address bits are always correct
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19. Efficiency vs. buffer size in a super pixel column
Expect the efficiencies to be even lower for chips 2 and 6 (located on both sides of chip 4)=> Efficiency drops very quickly below 99 %
Some losses are still caused by bugs (previous slide, last row)
Effect of the periphery on the efficiency must also be investigated before the overall efficiency can be obtained
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20. Conclusions and future work
Verilog code for super pixel column has been written and being verified (lots of bugs still exist)
After the verification, the code will be synthesized into a silicon level layout
The layout will then be simulated with the data from Gauss/Boole simulations
One of the main concerns is the area (when synthesized in IBM’s 130 nm process)
By combining the physics simulation data and the layout, good estimation of power consumption can be obtained (for active area)
All ideas and suggestions are also greatly appreciated!!!
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