1. Conditional-Sum Adders Parallel Prefix Network Adders
ECE 645: Lecture 3
Conditional-Sum Adders
and
Parallel Prefix Network Adders
FPGA Optimized Adders

2. Required Reading Behrooz Parhami,
Computer Arithmetic: Algorithms and Hardware Design
Chapter 7.4, Conditional-Sum Adder
Chapter 6.4, Carry Determination as Prefix Computation
Chapter 6.5, Alternative Parallel Prefix Networks

3. Add-Add-Multiplex
Carry Select Adder

4. Two-level k-bit Carry Select Adder

5. Add-Add-Multiplex (AAM) Carry Select Adder
+ stands for the Ripple Carry Adder
CCC stands for the Carry Computation Circuit
CR stands for the Carry Recovery Circuit

6. Carry Computation Circuit

7. Carry Recovery Circuit

8. Carry & Control Logic in Virtex 4

9. Carry & Control Logic in Virtex 5

10. Homework 2 - Bonus Analytical Problem:
Find analytically an optimal value of the word size, w, for which a 1024-bit AAM Carry Select Adder has the smallest latency.
Implementation Problem:
Find experimentally an optimal value of the word size, w, for which a 1024-bit AAM Carry Select Adder has the smallest latency.

11. Conditional-Sum
Adders

12. One-level k-bit Carry-Select Adder

13. Two-level k-bit Carry Select Adder

14. Conditional Sum Adder Extension of carry-select adder
One-level using k/2-bit adders
Two-level using k/4-bit adders
Three-level using k/8-bit adders
Etc.
Assuming k is a power of two, eventually have an extreme where there are log2k-levels using 1-bit adders
This is a conditional sum adder

15. Conditional Sum Adder: Top-Level Block for One Bit Position

16. Three Levels of a Conditional Sum Adder
xi+3
yi+3
xi+2
yi+2
xi+1
yi+1 xi yi
branch point
1-bit conditional sum block
concatenation
c=1
c=0
c=1
c=0
c=1
c=0
c=1
c=0 2 2 2 2 2 2 2 2 1 1
1+1 1 1 2 2 1 1 2 2 1 1
c=1
c=0
c=1
c=0 3 3 3 3 1
2+1 1 2 2 3 3
block carry-in determines selection 5
4+1 5
c=0
c=1

17. 16-Bit Conditional Sum Adder Example

18. Conditional Sum Adder Metrics

19. Parallel Prefix Network
Adders

20. Parallel Prefix Network Adders
Basic component - Carry operator (1) g p B” B’ B g” p” g’ p’
g = g” + g’p”
p = p’p”
(g, p) = (g’, p’) ¢ (g”, p”) = (g” + g’p”, p’p”)

21. Parallel Prefix Network Adders
Basic component - Carry operator (2) g p
overlap okay! B” B’ B g” p” g’ p’
g = g” + g’p”
p = p’p”
(g, p) = (g’, p’) ¢ (g”, p”) = (g” + g’p”, p’p”)

22. Properties of the carry operator ¢
Associative
[(g1, p1) ¢ (g2, p2)] ¢ (g3, p3) = (g1, p1) ¢ [(g2, p2) ¢ (g3, p3)]
Not commutative
(g1, p1) ¢ (g2, p2)  (g2, p2) ¢ (g1, p1)

23. Parallel Prefix Network Adders
Major concept
Given:
(g0, p0) (g1, p1) (g2, p2) … (gk-1, pk-1)
Find:
(g[0,0], p[0,0]) (g[0,1], p[0,1]) (g[0,2], p[0,2]) … (g[0,k-1], p[0,k-1])
block generate from index 0 to k-1
ci = g[0,i-1] + c0p[0,i-1]

24. Similar to Parallel Prefix Sum Problem
Given:
x x x … xk-1
Find:
x0 x0+x1 x0+x1+x2 … x0+x1+x2+ …+ xk-1
Parallel Prefix Adder Problem
Given:
x x x … xk-1
Find:
x0 x0 ¢ x1 x0 ¢ x1 ¢ x2 … x0 ¢ x1 ¢ x2 ¢ … ¢ xk-1
where xi = (gi, pi)

25. Parallel Prefix Sums Network I

26. Parallel Prefix Sums Network II (Brent-Kung)

27. 8-bit Brent-Kung Parallel Prefix Network

28. 4-bit Brent-Kung Parallel Prefix Network
2 –bit B-K PPN
s7’
s5’
s3’
s1’

29. 8-bit Brent-Kung Parallel Prefix Network Adder

30. Critical Path gi = xi yi pi = xi  yi 1 gate delay g = g” + g’ p”
p = p’ p”
2 gate delays C
ci+1 = g[0,i] + c0 p[0,i]
2 gate delays S
si = pi  ci
1 gate delay

31. Brent-Kung Parallel Prefix Graph for 16 Inputs

32. Kogge-Stone Parallel Prefix Graph for 16 Inputs

33. Parallel Prefix Network Adders
Comparison of architectures
Network 2
Brent-Kung
Hybrid
Kogge-Stone
Delay(k)
2 log2k - 2
log2k+1
log2k
Cost(k)
2k log2k
k/2 log2k
k log2k - k + 1
Delay(16) 6 5 4
Cost(16) 26 32 49
Delay(32) 8 6 5 57 80
Cost(32)
129

34. Latency vs. Area Tradeoff

35. Hybrid Brent-Kung/Kogge-Stone Parallel Prefix Graph for 16 Inputs

36. Parallel Prefix Sums Network I

37. Parallel Prefix Sums Network I – Cost (Area) Analysis
Cost = C(k) = 2 C(k/2) + k/2 =
= 2 [2C(k/4) + k/4] + k/2 = 4 C(k/4) + k/2 + k/2 =
= …. =
= 2 log k-1C(2) + k/2 (log2k-1) =
= k/2 log2k 2
C(2) = 1
Example:
C(16) = 2 C(8) + 8 = 2[2 C(4) + 4] + 8 =
= 4 C(4) + 16 = 4 [2 C(2) + 2] + 16 =
= 8 C(2) + 24 = = 32 = (16/2) log2 16

38. Parallel Prefix Sums Network I – Delay Analysis
Delay = D(k) = D(k/2) + 1 =
= [D(k/4) + 1] + 1 = D(k/4) =
= …. =
= log2k
D(2) = 1
Example:
D(16) = D(8) + 1 = [D(4) + 1] + 1 =
= D(4) + 2 = [D(2) + 1] + 2 =
= 4 = log2 16

39. Parallel Prefix Sums Network II (Brent-Kung)

40. Parallel Prefix Sums Network II – Cost (Area) Analysis
Cost = C(k) = C(k/2) + k-1 =
= [C(k/4) + k/2-1] + k-1 = C(k/4) + 3k/2 - 2 =
= …. =
= C(2) + (2k - 2k/2(log k-1)) - (log2k-1) =
= 2k log2k 2
C(2) = 1
Example:
C(16) = C(8) = [C(4) + 8-1] =
= C(2) = = 26
= 2· log216

41. Parallel Prefix Sums Network II – Delay Analysis
Delay = D(k) = D(k/2) + 2 =
= [D(k/4) + 2] + 2 = D(k/4) =
= …. =
= 2 log2k - 1
D(2) = 1
Example:
D(16) = D(8) + 2 = [D(4) + 2] + 2 =
= D(4) + 4 = [D(2) + 2] + 4 =
= 7 = 2 log

42. Parallel Prefix Network
High-Radix
Parallel Prefix Network
Adders
(GMU CERG Research)

43. Traditional Parallel-Prefix Network Adder

44. Kogge-Stone Parallel-Prefix Network

45. Brent-Kung Parallel-Prefix Network

46. High-Radix Parallel-Prefix Network Adder

47. Generate-Propagate-Sum (GPS) Unit

48. Sum Unit

49. Modular Addition

50. High-Radix Parallel-Prefix Network Modular Adder

51. Test Circuit for Benchmarking Adders and Modular Adders