1. Instruction Execution (Load and Store instructions)
ie := (
(op<4..0>= 1) : R[ra] ¬ M[disp], load register (ld)
(op<4..0>= 2) : R[ra] ¬ M[rel], load register relative (ldr)
(op<4..0>= 3) : M[disp] ¬ R[ra], store register (st)
(op<4..0>= 4) : M[rel] ¬ R[ra], store register relative (str)
(op<4..0>= 5) : R[ra] ¬ disp, load displacement address (la)
(op<4..0>= 6) : R[ra] ¬ rel, load relative address (lar)
Other instructions go here

2. Instruction Execution (Branch instructions)
ie := (
(op<4..0>= 8) : (cond : PC ¬ R[rb]), conditional branch (br)
(op<4..0>= 9) : (R[ra] ¬ PC,
cond : (PC ¬ R[rb]) ), branch and link (brl)

3. Instruction Execution (Branch instructions)
ie := (
(op<4..0>= 8) : (cond : PC ¬ R[rb]), conditional branch (br)
(op<4..0>= 9) : (R[ra] ¬ PC,
cond : (PC ¬ R[rb]) ), branch and link (brl)
cond := (
c3á2..0ñ=0 : 0, never
c3á2..0ñ=1 : 1, always
c3á2..0ñ=2 : R[rc]=0, if register is zero
c3á2..0ñ=3 : R[rc]¹0, if register is nonzero
c3á2..0ñ=4 : R[rc]á31ñ=0, if positive or zero
c3á2..0ñ=5 : R[rc]á31ñ=1 ), if negative

4. Instruction Execution (Branch instructions)
ie := (
(op<4..0>= 8) : (cond : PC ¬ R[rb]), conditional branch (br)
(op<4..0>= 9) : (R[ra] ¬ PC,
cond : (PC ¬ R[rb]) ), branch and link (brl)
This simply means that when c3<2..0> is equal to one of these six values, substitute the expression on the right hand side of the : in place of cond
cond := (
c3á2..0ñ=0 : 0, never
c3á2..0ñ=1 : 1, always
c3á2..0ñ=2 : R[rc]=0, if register is zero
c3á2..0ñ=3 : R[rc]¹0, if register is nonzero
c3á2..0ñ=4 : R[rc]á31ñ=0, if positive or zero
c3á2..0ñ=5 : R[rc]á31ñ=1 ), if negative

5. Instruction Execution (Arithmetic and Logical instructions)
ie := (
(op<4..0>=12) : R[ra] ¬ R[rb] + R[rc],
(op<4..0>=13) : R[ra] ¬ R[rb] + c2á16..0ñ {sign extend},
(op<4..0>=14) : R[ra] ¬ R[rb] - R[rc],
(op<4..0>=15) : R[ra] ¬ - R[rc],
(op<4..0>=20) : R[ra] ¬ R[rb] & R[rc],
(op<4..0>=21) : R[ra] ¬ R[rb] & c2á16..0ñ {sign extend},
(op<4..0>=22) : R[ra] ¬ R[rb] ~ R[rc],
(op<4..0>=23) : R[ra] ¬ R[rb] ~ c2á16..0ñ {sign extend},
(op<4..0>=24) : R[ra] ¬ ! R[rc],

6. Instruction Execution (Arithmetic and Logical instructions)
ie := (
(op<4..0>=12) : R[ra] ¬ R[rb] + R[rc],
(op<4..0>=13) : R[ra] ¬ R[rb] + c2á16..0ñ {sign extend},
(op<4..0>=14) : R[ra] ¬ R[rb] - R[rc],
(op<4..0>=15) : R[ra] ¬ - R[rc],
(op<4..0>=20) : R[ra] ¬ R[rb] & R[rc],
(op<4..0>=21) : R[ra] ¬ R[rb] & c2á16..0ñ {sign extend},
(op<4..0>=22) : R[ra] ¬ R[rb] ~ R[rc],
(op<4..0>=23) : R[ra] ¬ R[rb] ~ c2á16..0ñ {sign extend},
(op<4..0>=24) : R[ra] ¬ ! R[rc],
and
add
sub
addi
neg or
andi
ori
not

7. Instruction Execution (Shift instructions)
ie := (
(op<4..0>=26) : R[ra]á31..0 ñ ¬ (n α 0) © R[rb] á31..nñ,
(op<4..0>=27) : R[ra]á31..0 ñ ¬ (n α R[rb] á31ñ) © R[rb] á31..nñ,
(op<4..0>=28) : R[ra]á31..0 ñ ¬ R[rb] á31-n..0ñ © (n α 0),
(op<4..0>=29) : R[ra]á31..0 ñ ¬ R[rb] á31-n..0ñ © R[rb]á n ñ,
where
n := ( (c3á4..0ñ=0) : R[rc],
(c3á4..0ñ¹0) : c3 á4..0ñ ),
Notation: α means replication
© means concatenation

8. Instruction Execution (Shift instructions)
ie := (
(op<4..0>=26) : R[ra]á31..0 ñ ¬ (n α 0) © R[rb] á31..nñ,
(op<4..0>=27) : R[ra]á31..0 ñ ¬ (n α R[rb] á31ñ) © R[rb] á31..nñ,
(op<4..0>=28) : R[ra]á31..0 ñ ¬ R[rb] á31-n..0ñ © (n α 0),
(op<4..0>=29) : R[ra]á31..0 ñ ¬ R[rb] á31-n..0ñ © R[rb]á n ñ,
shr
shra
where
n := ( (c3á4..0ñ=0) : R[rc],
(c3á4..0ñ¹0) : c3 á4..0ñ ),
shl
shc
Notation: α means replication
© means concatenation

9. Instruction Execution (Miscellaneous instructions)
ie := (
(op<4..0>= 0) : , No operation (nop)
(op<4..0>= 31) : Run ¬ 0, Halt the processor (Stop)
); iF );
Instruction Execution ends here

10. The basic D Flip-Flop

11. The basic D Flip-Flop Q output Data input Enable input Active low
Clock input
Active low
clear input

12. The n-bit register Definition: a group of FFs operating synchronously
Can be formed by using n D flip-flops
Connect the clock inputs of DFFs together (and enables also)
Clock to DFFs has to be free running, especially for dynamic gates; use En to load registers

13. A 4-bit register: circuit

14. A 4-bit register: our symbol
Inputs
Clock
Enable
Outputs

15. A 4-bit register: test circuit

16. A 4-bit register: waveforms
Inputs
Outputs

17. A 4-to-1 MUX: our symbol
Inputs 3 2 1
output

18. A 4-to-1 MUX: test circuit

19. A 4-to-1 MUX: waveforms 3 1

20. Tri-state buffers: circuit symbol
ENABLE
Data Input
Data Output
Don’t care
Data input
Enable
Data output X Z 1

21. A 4-bit tri-state buffer unit (our symbol)

22. A 4-bit tri-state buffer unit (test circuit)