1. Cost &Personnel Estimates Project Organization
Mel Shochet
for the FTK group
December 2, 2010
FTK Design review

2. Material Cost Estimate
Cost basis
Our engineers have a great deal of experience designing and building large hadron collider trigger systems
CDF level-1 trigger and upgrades
CDF calorimeter trigger upgrade
CDF SVT and upgrades
CDF muon trigger and 2-track trigger
CDF level-2 trigger upgrade
ATLAS ROI Builder
The conceptual design in the Technical Proposal is described in detail including the needed FPGAs, memory chips, and interboard data transfer.
December 2, 2010
FTK Design review

3. We and our engineers (in the US, the head of the Chicago Engineering Development Group; in Italy, the technical staff, Lanza, and Piendibene) estimated the cost for each board type:
PC boards based on our recent experience with similar size and complexity boards
the FPGAs and memory chips in the Technical Proposal
an estimate for the rest of the parts based on similar recent boards
an estimate for board stuffing based on similar recent boards
separate estimates for prototypes and production
Spares are included
[For the U.S. responsibilities, the funding agencies were given estimates that included contingency:
none on racks, crates, and fibers (based on industry prices)
15% on the HOLAs (advanced engineering stage)
30% on all other boards]
December 2, 2010
FTK Design review

4. We did not take into account the typical drop in the cost of FPGAs and memory of a given capability between now and when production would likely begin (~2013). However changes in the $€ exchange rate could counteract that drop.
For the AM chips for phase I, we used Europractice prices as of 2012, again not taking into account how prices for a given process tend to drop with time. In this case, exchange rate fluctuations, which are not predictable, could be even more important.
December 2, 2010
FTK Design review

5. Material Cost Estimate k€ [1€ = $1. 40, was $1
Material Cost Estimate k€ [1€ = $1.40, was $1.50 in the TP] (no contingency)
Infrastructure units cost
Racks
Crates with CPUs & power supplies
ROD-to-FTK fibers
Dual-output HOLAs
IntraFTK fibers and cables
FTK boards
Data Formatter motherboard
Data Formatter mezzanines (pixel & SCT)
Processor AUX card (DO, TF, HW)
Processor main card
LAMB
TF/HW final board
ROD
December 2, 2010
FTK Design review

6. Total except for prototypes: 2.6 M€
AM chip (major change after CERN ICHEP presentation showing large pile-up as soon as 2013)
MPW submission k$
small production k$
MLM masks for pilot run (6 metal layer project) 500 k$
production wafers (pilot run, 6 metal layer project) 295 k$
TOTAL: 750 k€
Total except for prototypes: M€
Prototypes (costed separately) k€
This does not include R&D for a phase II 3D AM chip, for which we are seeking generic R&D support since it could also be used for a phase II level-1 track trigger for ATLAS and/or CMS.
December 2, 2010
FTK Design review

7. What’s missing? ROS’s: Processor units:
We didn’t know how many we needed or who pays for them. The simplest solution would require 6 ROS’s each with 1 ROBIN. (25 k€)
[However, if we don’t pay for the racks, the budget drops by 16 k€.]
Processor units:
There is a discrepancy between the number of AM boards and AUX cards. Our original plan had 16 processor units per core crate. The current simulation shows that 12 would be sufficient for the planned maximum phase I pile-up of 41.5.
For the AUX cards (U.S. responsibility), we cost 16/crate to have the maximum we might need. (budget drops by 143 k€ if 12 are needed)
For the AM boards, we used 12/crate to make room for the added AM chip cost. (budget increases by 138 k€ if 16 are needed)
There will be more certainty after we analyze real data and we know whether the accelerator can reach 25 ns bunch spacing or must stay at 50 ns and use the larger tune-shift & aperture margin to increase the bunch proton intensity.
December 2, 2010
FTK Design review

8. Personnel (FTE months)
Engineering design testing
Data Formatter
Processor AUX
HOLA
Final core crate board
ROD
Data Formatter mezzanine
Processor main board
LAMB
AM chip
December 2, 2010
FTK Design review

9. (Physicist FTE months) firmware testing
Strict code writing format, documentation, and long-term maintenance. Ted Liu (Fermilab), who led a major CDF trigger upgrade, will set the standards.
(Physicist FTE months) firmware testing
Data Formatter
Processor AUX
HOLA
Final core crate board
ROD
Data Formatter mezzanine
Processor main board
LAMB
Integration & commissioning months
Online software (monitoring, initialization, error recovery) 36 months
December 2, 2010
FTK Design review

10. Personnel Argonne: G. Drake, J. Proudfoot, J. Zhang
Bologna: F. Giorgi, M. Villa, A. Zoccoli
Chicago: M. Bogdan, A. Boveia, F. Canelli (&FNAL), Y. Chang, A. Kapliy, Y.K. Kim (&FNAL), C. Melachrinos, M. Shochet, F. Tang, J. Tang, J. Tuggle, J. Webster
Fermilab: J. Hoff, T. Liu, B. Penning, M. Verzocchi, J.Y. Wu
Frascati: A. Annovi, M. Beretta, G. Volpi
Illinois: M. Kasten, A. McCarn, M.S. Neubauer
Milan: A. Andreani, M. Citterio, V. Liberali, C. Meroni, A. Stabile
Northern Illinois: G. Blazey
Pavia: A. Lanza, A. Negri, V. Vercesi
Pisa: F. Crescioli, M. Dell’Orso, P. Giannetti, M. Piendibene, C. Roda, I. Sacco
Waseda: N. Kimura, K. Yorita
December 2, 2010
FTK Design review

11. Associative Memory personnel include some people outside FTK and even ATLAS.
University of Heidelberg: A. Schoening, H. Soltveit
University of Ferrara: R. Tripiccione
University of Perugia: D. Malagotti
December 2, 2010
FTK Design review

12. M. Shochet, Project Manager P. Giannetti, Deputy Project Manager
Organization
M. Shochet, Project Manager
P. Giannetti, Deputy Project Manager
TASK LEADERS
Hardware
HOLA: M. Shochet (Chicago)
Data Formatter: B. Penning (Fermilab)
Clustering mezzanine: M. Beretta (Frascati)
AMBoard: M. Citterio (Milan)
LAMB: A. Lanza (Pavia)
AMBoard & LAMB firmware: M. Piendibene (Pisa)
AM chip: A. Annovi (Frascati)
after 1st submission V. Liberali (Milan)
AUX board: F. Canelli, M. Shochet (Chicago)
Final core crate board: M. Neubauer (Illinois)
ROD: J. Zhang (Argonne)
December 2, 2010
FTK Design review

13. Firmware standards: T. Liu (Fermilab)
Firmware is the responsibility of the institute designing the board.
System Integration:
Tests & board integration in the vertical slice M. Piendibene (Pisa)
DAQ integration: vertical slice/Demonstrator F. Crescioli (Pisa)
Rack integration A. Lanza (Pavia)
(including power supplies, cooling, and safety)
Interface to level-2 J. Zhang (Argonne)
FTK simulation G. Volpi (Marie-Curie
Frascati-Chicago)
December 2, 2010
FTK Design review

14. Coordination
Up to now, we have had weekly meetings (1-3 hours each week) to review and give guidance on all aspects of the work:
performance & optimization
hardware
software
We will now move to independent weekly meetings in each activity area so that the work can be discussed in more detail.
AM chip
boards
vertical slice
simulation studies and data analysis
December 2, 2010
FTK Design review

15. For each board, we plan a series of internal reviews.
initial specifications before starting hardware design
updated specifications and preliminary hardware work
full design review before prototype manufacture
review of tested prototype
There will be similar reviews for firmware & online software.
December 2, 2010
FTK Design review