1. A 1 V RF front-end for both HIPERLAN2 and 802.11a
T. Taris, JB. Begueret, H. Lapuyade, Y. Deval
IXL laboratory, University of Bordeaux 1, Talence, France

2. OUTLINE HIPERLAN2 and 802.11a requirements
Wireless mass market design constrains
LNA
MIXER
RF Front-end
Measurement results
Conclusions

3. HIPERLAN2 and 802.11a requirements
Communication standard
HiperLAN2 and a
gain
10 dB
Noise Figure
ICP1
-21 dBm
IIP3
-10 dBm
Frequency band
GHz
Mixer
LNA
VGA
PBF
PBF LO

4. Wireless mass market constrains
Wireless applications Mass market
CMOS VLSI
analog design
Power aware systems
Low Power / Low Voltage
<10 mW / ~1V

5. Maximum signal collected
LNA
Ftot = FLNA+(Fmixer-1)/GLNA
Input matching
Low noise figure
Low power
&
Low voltage
Maximum signal collected
Ftot = FLNA+(Fmixer-1)/GLNA
Gain

6. Inductive Degeneration
LNA
Tuned Load
Good Linearity
out
Reduce
Miller Effect Lg
MLNA RF
bias Ls
Inductive Degeneration
Low Noise Figure
50 input matching

7. Mixer Mixing Gain operation Linearity Principle efficiency Low power &
Low voltage
Mixing principle brought into play
Voltage dynamic range trade-off
Linearity

8. Mixer Low-pass filter behavior High-pass filter behavior
VFI
High-pass filter behavior
VLO
bias
VRF
In saturation region:
Assuming:

9. RF Front-End RF LO FI R
Cd2
Rconv
Cd1
Mmix
MLNA
LNA
Mixer

10. Isolation LO>RF = -34 dB
Measurement results
S11 = -26 dB
Isolation LO>RF = -34 dB
Inductive degeneration matching
Due to closeness of RF and LO port

11. Measurement results Gain = 10 dB @ 1 V ICP1=-9 dBm & IIP3=0 dBm8 7 6 5 4 3 2 1
Supply Voltage (V)
0.8
0.9 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Gain = 10 1 V
ICP1=-9 dBm & IIP3=0 dBm
Good input matching
Architecture well suited to low voltage
Efficiency of resistor load
Bypass filter behavior

12. Measurement results Measurment results Requirements Frequency band
 GHz
Supply
1 V NC
Gain
10 dB
Noise Figure
8 dB
Current consumption
6 mA
ICP1
-9 dBm
-21 dBm
IIP3
0 dBm
-10 dBm
Isolation LO>RF
-34 dBm
> -30 dBm

13. Conclusions
Fulfill successfully both HIPERLAN2 and a requirements
Operating under 1V and consuming only 6 mA, it is well suited to low power/low voltage applications
implemented in CMOS VLSI technologie its weak bulkiness (750µm500µm ) dedicates it to System On a Chip (SOC) applications

14. Perspectives Improve isolation between LO and RF port
Architecture without inductance (matching trade-off)
Enhance the conversion gain (linearity trade-off)