1. Front-end and VME / VXI readout electronics for ASICs
Ch. THEISEN – CEA Saclay
May 25th, 2007
- Christophe THEISEN - INTAG Workshop GSI

2. Context
ASICs and readout electronics for the MUSETT Silicon detectors and other Si strip detectors (MUST II, annular Silicon detector for Coulex)
Large number of channel. Integrated electronics mandatory (MUSETT = 1024 channel).
May 25th, 2007
- Christophe THEISEN - INTAG Workshop GSI

3. Electronics for one MUSETT detector
COFEE (x4)
Analogue
Bus
MUVI or CVM (x4) LV 4
Readout
ATHED
Trigger
CAEN SY 2527
Slow Control HV
I2C 64
strips
Slow Control
Slow Control
Silicium
Cooling LAUDA
Proline RP 845 C
May 25th, 2007
- Christophe THEISEN - INTAG Workshop GSI

4. ASICs : ATHED (Saclay design)
Based on MATE ASICs for MUST II
May 25th, 2007
- Christophe THEISEN - INTAG Workshop GSI

5. 16 channels (Energy + Time)
0.8 μm BiCMOS AMS 6×6mm2
16 channels (Energy + Time)
Dynamics : +/-10MeV; +/-45MeV; +/-225MeV; +/-1GeV
Shaping : 1 or 3 μs
Energy resolution : 16 keV for Cdet = 65 pF
Multiplex output : analogue differential bus 2 MHz
Slow Control: serial I2C; DAC, channel enable, channel test, shaping time, readout mode, …
Energy
Time
C.S.A
E16
T16
start16
Idet16
V.I.C
Slow Control
OR start
DAC Discri thresh E1 T1
start1
Idet1
Stop
Start
Test
I2C
Request
Analogue
Data
Hold
Reset In
16 Channels
ATHED
May 25th, 2007
- Christophe THEISEN - INTAG Workshop GSI

6. Front-end electronics : COFEE (IPNO design)
COulex Front-End Electronics
Based on MUST II MUFEE
4 ASICs / board
1 analogue bus / ASIC
Size 12 x 5 cm2
Slow control : I2C
Provides HV to detectors (daughter boards)
May 25th, 2007
- Christophe THEISEN - INTAG Workshop GSI

7. Readout Two readout for MUSETT
Laboratory DAQ : CVM VME cards : “light” acquisition
Experiment DAQ : MUVI VXI cards : for GANIL environment
May 25th, 2007
- Christophe THEISEN - INTAG Workshop GSI

8. CVM VME card (Saclay design)
Multipurpose card for ASICs readout
4 analogue bus input = 4 ASICs with COFEE = 64 channels
USB slow control through STUC probe (Cypress micro controller, Virtex II FPGA).
VME or USB readout
Possibility to correlate VME cards (front panel trigger signals and clock).
14 bits ADCs
48 bits timestamp (100 MHz)
Status:
Two prototypes tested
VME readout in progress
Waiting for Cofee front-end electronics before production.
May 25th, 2007
- Christophe THEISEN - INTAG Workshop GSI

9. CVM
May 25th, 2007
- Christophe THEISEN - INTAG Workshop GSI

10. CVM slow control and DAQ
LabView, VHDL, C daemon. XML data output. Root tools to be developed
May 25th, 2007
- Christophe THEISEN - INTAG Workshop GSI

11. May 25th, 2007
- Christophe THEISEN - INTAG Workshop GSI

12. MUVI (Ganil design) MUST VXI 4x4 analogue bus input.
For 4 Cofee cards (16 ASICs) = 128 strips = 1 MUSETT detector (for 4 MUST II detectors since 1 bus/Mufee)
CAS mezzanine converter
Free running mode : all bus running independently and trigger-less
Time stamp with ATOM / GAMER / CENTRUM cards (48 bits, 10 ns resolution).
Full integration into the GANIL DAQ – DAS GUI
May 25th, 2007
- Christophe THEISEN - INTAG Workshop GSI

13. MUVI
ATOM
CAS
May 25th, 2007
- Christophe THEISEN - INTAG Workshop GSI

14. Status ASICS ready Cofee being tested
CVM being tested. Next : tests with Cofee
Test of Si + Cofee + CVM soon
MUVI ready for production
May 25th, 2007
- Christophe THEISEN - INTAG Workshop GSI