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Low-power Digital Signal Processing for Mobile Phone chipsets
Mike Lewis AMULET group
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GSM (digital) mobile phones
Huge (and increasing) market Highly competitive Battery size and lifetime are key
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Low power DSP for GSM Chipsets
GSM Chipsets typically based on microprocessor + DSP GEM301 baseband processor: ARM + OAK Microprocessor performs control tasks DSP performs intensive calculations How is power consumption divided?
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Sources of power consumption
In GEM301 chipset: DSP consumes 1mA per MIP Maximum DSP activity of 36 MIPS Maximum total consumption 55mA DSP consumes 36mA, 65% of total current DSP power consumption will increase with increased algorithmic complexity DSP power particularly important for wireless LANs (e.g. Bluetooth)
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What’s needed from the DSP?
>100 MIPS throughput OAK DSP maintains 40 MIPS for half-rate More intensive coding algorithms More additional applications required Choose 4x speed increase:160 MIPS
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Sources of power consumption
Program and data memory access Power dissipated by RAM Power dissipated in system buses Calculations on data Transitions on internal buses Transitions within arithmetic units Control overhead
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How to keep the power down...
Parallel structure Keep processing rate of each unit down Turn excess speed into power reduction VLIW preferable for low power Parallelism exploited by programmer But… VLIW involves long instructions!
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Compressed Instructions
DSP activity characterized by regular repetition of fixed algorithms Store the instructions in configuration memories internal to the DSP Execute instructions with 32 bit word System speed remains at 40MHz
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Compressed instructions
Instructions stored in each functional unit Split into operand and opcode memories Operands: register selections / immediates Opcode: operation selection Instruction buffer handles looping Complex algorithms can be executed with only one pass from program memory
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How to keep the power down… (2)
Use a large register file to reduce accesses to data memory Simple RISC-like load-store architecture Register file segmented into two 128 word banks (X and Y to match memory) Maximum data reuse Data accessed by 7-bit index register rather than 24-bit address register Results go to ALU accumulators
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How to keep the power down… (3)
Sign-magnitude number system chosen Investigation showed a power reduction of 10-50% over 2’s complement scheme Power saving particularly accentuated when long buses are driven
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Asynchronous design Synchronous design
All activity synchronised by common clock Latch
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How to keep the power down… (4)
Asynchronous design No clock distribution network No need for clock gating Exploit end-of-block idle time Reduced EMC problems Modular design
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How to keep the power down… (5)
DSPs are good at number-crunching… less good at control code Use DSP as a coprocessor Limited support for context switches Microprocessor prepares tasks and directs the DSP to perform them Simple interrupt structure to synchronize on arrival of data
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A low-power DSP architecture
Fetch unit- autonomous instruction fetch X/Y mem Register Bank (2x128x16 bit) Load-store unit P mem Fetch Buffer ALU ALU ALU ALU VLIW mem VLIW mem VLIW mem VLIW mem Decode int0, int1, nmi Operand Opcode Index reg. Index register values
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A low-power DSP architecture
Instruction buffer: 32 entry FIFO also handles loops X/Y mem Register Bank (2x128x16 bit) Load-store unit P mem Fetch Buffer ALU ALU ALU ALU VLIW mem VLIW mem VLIW mem VLIW mem Decode int0, int1, nmi Operand Opcode Index reg. Index register values
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A low-power DSP architecture
Decode instruction, read VLIW operand X/Y mem Register Bank (2x128x16 bit) Load-store unit P mem Fetch Buffer ALU ALU ALU ALU VLIW mem VLIW mem VLIW mem VLIW mem Decode int0, int1, nmi Operand Opcode Index reg. Index register values
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A low-power DSP architecture
Substitute and update index registers X/Y mem Register Bank (2x128x16 bit) Load-store unit P mem Fetch Buffer ALU ALU ALU ALU VLIW mem VLIW mem VLIW mem VLIW mem Decode int0, int1, nmi Operand Opcode Index reg. Index register values
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A low-power DSP architecture
Read registers and VLIW opcode X/Y mem Register Bank (2x128x16 bit) Load-store unit P mem Fetch Buffer ALU ALU ALU ALU VLIW mem VLIW mem VLIW mem VLIW mem Decode int0, int1, nmi Operand Opcode Index reg. Index register values
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A low-power DSP architecture
Perform operation X/Y mem Register Bank (2x128x16 bit) Load-store unit P mem Fetch Buffer ALU ALU ALU ALU VLIW mem VLIW mem VLIW mem VLIW mem Decode int0, int1, nmi Operand Opcode Index reg. Index register values
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Conclusions Mobile communications has special requirements from the DSP Multi-level power reduction strategy should dramatically reduce power Async design will give simple power management and low EM interference DSP architecture fully designed, circuit level design underway So, to conclude; Mobile communication devices require low power consumption from the DSP. The tasks required from the DSP are quite specialised, and so a number of power saving strategies are possible which are implemented in the new DSP architecture. Power reduction is a multi-level process: there’s no ‘magic bullet’ that will give low power consumption. However, the strategies adopted should dramatically reduce power consumption. A simulation model of this new architecture has been completed, and work is now underway on the circuit-level design. So, we hope soon to be able to demonstrate how this new DSP can prolong the battery life of the next generation of mobile products! OK, does anybody have any questions?
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