1. Counting Mode DAQ for Compton
Shujie Li (presenting)
Bob Michaels, Alexandre Camsonne
Hanjie Liu, Scott Barcus (VETROC)
Polarimetry Meeting
Nov 21, 2016

2. Compton Asymmetry E=3.484 GeV From M. Friend Thesis, p57
The idea behind counting mode compton is very simple: count the number of signals with +/- helicity to get the overall helicity. And if the size of photon signal, is also measured, one can bin on energy to hopefully reproduce a nice curve as shown on the right.
From M. Friend Thesis, p57

3. Compton Asymmetry Deadtime? Signals pileup? E=3.484 GeV
Trigger rates: 10k -100 kHz
However, high quality counting is difficult because of the very high rates of compton scattering events. It causes deadtime, and signals pileup, results in large systematic error.
Why not prescaling???
Deadtime?
Signals pileup?
From M. Friend Thesis, p57

4. DAQ systems for Compton data:
“new” Counting Mode is based on CODA3 with pipelining electronics and Intel PC
CMU DAQ works well, presently based on vxWorks cpu
Counting vs Integrating has different advantages.
To avoid the disadvantage of counting mode, people developed the integrating DAQ fo Hall A compton. It has been sitting in the hall and taking data for a while, and works well.
While the integral DAQ is our primary system, people are trying to bring the counting mode back with the Jlab-designed pipelining electronics.

5. Exists, being tested in Hall A with photon detector
The new electronics include Flash ADC for the photon detector, which has been set up in the hall in the past summer, and is taking data in the fall. The Vetroc card is currently in the GRINCH detector test stand.
Exists, under development in the GRINCH chrenkov detector test stand

6. Counting Mode DAQ deadtime-free? Flash ADC 250 MHz: Made by JLab
Signal Distribution
Trigger Interface
Flash ADC
SCALER
Flash ADC 250 MHz:
Made by JLab
4,000 dollars
16 channels
Ring buffer with up to 8 μs latency
Double buffer allows taking and processing data at the same time
Send data by block (1-256 triggers)
One FADC card can take 16 signals, costs 4000 dollars. Each channel has separate ring buffer to continuously taking signal even when the signal is processing.
Instead of sending data trigger by trigger, FADC can send a block of data at once for higher data rate and shorter busy time.
deadtime-free?

7. Trigger Signal CPU FADC TI SD Busy backplane
To reduce the amount of data generated at high trigger rates, the module has the
capability of identifying pulses within the trigger window and reporting computed
quantities (pulse integral, pulse time) instead of raw data samples or simple sums of raw
samples.
Data from ADC are stored continuously in circular buffer until Trigger input becomes
activeThe data that was stored from the time that the Trigger occurs back to the
time specified by Programmable Latency within the Programmable Trigger Window are
processed.
While data are being processed, ADC FPGA will continue storing incoming ADC data
with no loss of data.
backplane

8. Only the integral is recorded
Trigger
Signal
Latency
CPU TI SD
FADC
Trigger Window
Busy
threshold
To reduce the amount of data generated at high trigger rates, the module has the
capability of identifying pulses within the trigger window and reporting computed
quantities (pulse integral, pulse time) instead of raw data samples or simple sums of raw
samples.
Data from ADC are stored continuously in circular buffer until Trigger input becomes
activeThe data that was stored from the time that the Trigger occurs back to the
time specified by Programmable Latency within the Programmable Trigger Window are
processed.
While data are being processed, ADC FPGA will continue storing incoming ADC data
with no loss of data.
This DAQ system with FADC is expected to have very small if not zero deadtime at 100k, which allows us to measure asymmetry in high precision.
backplane
Only the integral is recorded

9. test mode Helicity from pulse generator
Asymmetry from V2F box ,with 250 kHz, 1.1% (0.88%) asymmetry
Random pulser (up to 100 kHz) to push system to the limit
Compare FADC and SCALER counts to get deadtime
In test mode, a 1 k helicity is generated by the pulser generator, then the square wave goes through the voltage to frequency box to produce 1.1% asym. Then signal then coupled with random signal to mimic “real world” signals. Since the asym box signal is too high for fadc, when only take a sample of it to send to scaler and fadc. The signal with + , - helicity are selected and sent to fadc as well.

10. test mode
Dt of signal can be calculated in two ways: comparing the scaler and fadc counts. Or looking at deadtime recorded by TI.
Plot shows dt as a function of random frequency. Dt from TI and FADC agree with each other. DT from asym signal behaves different since 250k is on the edge of the system capability.
But in general the dt is small at 20k, and <5% at 100k.

11. Test mode Asymmetry (%) Random frequency
Once DT is know, we can perform dt correction given fadc data to get real asym.
The correction doesn’t work well now b/c of low stats and asym box high freq. need to redesign the test.
Random frequency

12. Production mode Send BCM, CAVITY, HELICITY, MPS to FADC and scaler
Copies of photon signal and trigger from CMU DAQ
RUN 5609:
Date: Nov 07
Beam energy: 8518 GeV
Beam current: 10 us
Signal rates: ~7.5 kHz
Deadtime: ~ 0
QUAD
Helicity recorded by scaler has the correct pattern
From R. Michael

13. Production mode Send BCM, CAVITY, HELICITY, MPS to FADC and scaler
Bcm and cavity info from scaler and epics align well, scaler info has better resolution??
EPICS
From R. Michael

14. Production mode Send BCM, CAVITY, HELICITY, MPS to FADC and SCALER
Use BCM, cavity information to select events
Need to assign helicity to every signal
More study on deadtime
Successfully seeing compton spectrum. Next step is to match helicity
From R. Michael

15. What is a VETROC ? ( Vxs – based Electron Trigger and ReadOut Controller )
A module built by the JLab DAQ group
Like a TDC
Pipelining -- zero ( very little ) deadtime
Feeds data to a GTP across backplane. ( GTP also built at JLab)
GTP = Global Trigger Processor
GTP has FPGA programmed to form a trigger
based on pattern of hits in VETROC
Vetroc built by JLAB follow the similar pipelining philosophy as fadc. Vetroc can take trigger from external cable as TDC, but can also work with GTP witch will scan the data from vetroc to find the programmable trigger condition.
VETROC
GTP

16. VETROC Specs VETROC GTP Resolution : 1 nsec (our board) can be 20 psec
128 channels per board, 17 boards fit in crate
Bandwidth: 4 Gbit/sec
Can accept front-panel trigger, or can feed its data to GTP to form a trigger at 30 MHz
Readout speed – observations:
0 deadtime for kHz with 5 hits
250 kHz with 1 hit
Vetroc cost ~1k for 128 channels, has 1ns resolution, and almost 0 deadtime.
VETROC
GTP

17. GRINCH Test Stand Uses VETROC Similarly to how Compton Edet would
Scott Barcus
Carlos Gayoso
Ben Raydo
Evan McClellan
Data to vetroc to gtp to form trigger , go back to vetroc to convert to ecl, then send to TI

18. VETROC data from GRINCH Setup -- an example
PMT data processed by NINO cards. Light from LED. Two peaks are
leading and trailing edges. Trailing edge wider as expected.
Data example
Trigger on edges

19. Conclusions -- Counting Mode DAQ
Counting mode FADC DAQ for photons is being deployed
VETROC for electrons being used in a GRINCH test stand
Next year we’ll merge the above two, in a test stand
Future direction:
Can have a JLab FADC with accumulators alongside the counting FADC
Can have broad general use, e.g. SBS or SOLID.

20. Thank you

21. Deadtime with 250 kHz asym box signal