1. By Jonathan Bolus and Stuart Wooters
A Comparison Between Sub-threshold and Adiabatic Power Saving Techniques
By Jonathan Bolus and
Stuart Wooters

2. Carry Look Ahead Adder

3. Power Comparison of different VDD

4. Power Consumption Comparison with VDD=1

5. Sub-threshold Summary
Energy Consumption: 7.18 fJ/addition
f = 20 MHz
Power Consumption: nW
Number of Devices: 1230

6. ECRL Efficient Charge Recovery Logic
Essentially Differential Cascode Voltage Switch Logic (DCVSL).
VDD replaced by power clock:

7. Clock Timing

8. ECRL Inverters

9. Power Consumption

10. Adiabatic Adder Summary
Energy Consumption: 300 fJ/addition
f = 20 MHz
Power Consumption: 6 uW
Number of Devices: 1208

11. Conclusions
Adiabatic is not as affective at small values of VDD (lower than 2V). This is evident in the 90nm technology we used.
Sub-threshold saved 26x the power compared to VDD=1

12. References
A 0.5V, 400MHz, V/sub 00/-hopping processor with zero-V/sub TH/ FD-SOI technology
Kawaguchi, H.; Kanda, K.; Nose, K.; Hattori, S.; Dwi, D.; Antono, D.; Yamada, D.; Miyazaki, T.; Inagaki, K.; Hiramoto, T.; Sakurai, T.;
Solid-State Circuits Conference, Digest of Technical Papers. ISSCC IEEE International
2003 Page(s): vol.1
Digital Object Identifier /ISSCC
An Efficient Charge Recovery Logic Circuit
Yong Moon, and Deog-Kyoon Jeong;
IE Journal of Solid-State Circuits, Vol, 31, No.4, April 1996