1. Low Power Very Fast Dynamic Logic Circuits

2. Clocked CMOS (C2MOS) vs. Precharged CMOS
Clocked CMOS ; simultaneous switching of PMOS and NMOS switches.
-> (SP, SN) obtained by removing one switch (phase)
Precharged CMOS;
-> precharge is followed by evaluation by merging switch TR’s into one phase, i.e., removing one phase
-> domino or NORA (PP, PN) obtained by removing one signal transistor

3. C2MOS Logic
Fig.1
[Ref] J. Yuan and C. Svensson, high-speed CMOS Circuit technique, IEEE J. Solid-State Circuits, vol. 24, pp.62-70, Feb

4. NORA dynamic CMOS uses a true
C2MOS Logic
uses four clock phases
No overlaps between phi 1 and phi 2
Serious difficulty in speed increase when clock skew occurs
NORA
uses phi and ~phi only.
No race problem due to clock skew if condition of even # of inversions between stages is obeyed.

5. NORA ; Dynamic CMOS
NORA terminated by a C2MOS stage for synchronization
Fig.2

6. (Method 1) for removing ~clock ; Doubled N-C2MOS & P-C2MOS (Non-precharged type)
Fig.3

7. Logic arrangements in Non-precharged type
Fig.4

8. (Method 2) Split-output Latch stages
Fig.5

9. (Method 3) removing ~clock Precharged type
Fig.6

10. From C2MOS to four TSPC basic stages (SP, SN, PP, PN)
1. xN or xP depending on NMOS(xN) or PMOS(xP) as middle TR
2. Standard (Sx) vs. Precharged (Px)

11. TSPC latches ; should end with standard type stage
1) Non-precharged type latch ;
Standard + Standard
2) Precharged type latch ;
Precharged + Standard
SN+SN
SP+SP
SP+PP
SN+PN

12. Split-output Latches 1. Needs minimal (5) TR’s
2. Threshold loss at one gate causing leakage problems

13. Non-classic single-clock flip-flops
Precharged
N-type latch SP
1. Small # of TR’s
2. Inverted output
3. Delay of master (p-block) is
comparable to that of slave

14. t
Sampling
phase
Latching
phase
-ve (+ve)
edge triggered

15. Putting full latch (non-transparent during latching) at the input or output
Still maintaining TSPC
Equivalent to NMOS clocked by phi

16. Dynamic CVSL latch

17. Dynamic ratio-insensitive differential latch

18. Static (RAM type) Latches

19. Differential TSPC Latches
Use only a single clocked TR to reduce power
faster
Move clocked
TR to top
Add 2 minimal-size
NMOS TR

20. Various Flipflops

22. Power Delay Product

23. Embedding logic
Block is a latch, either PS (Precharge + Standard) or SS type.
It can be non-classical with only a single S stage

24. Double pipeline mux dmux Remove to halve mux & dmux time dmux time
Pipeline period
Pipeline period

25. CDPD (Clock and Data Precharge Dynamic) Logic
Clock needed
Precharge to intermediate node
Inverters needed
Long latency
Output is precharged low with high input.
Output taken from NMOS drain
No charge sharing
No clocking -> less power
Less transistors
Less latency

26. CDPD Chains
Even (Odd) number of alternating H/L and L/H blocks between same (different) type blocks
Domino inverters removed
Minimal # of clocked devices
Skewed precharging reduces peak current.
Both high and low clock
periods are used.

27. With A=high, B=low,
charge sharing occurs
Between X and output. x
With A=high, B=low,
charge sharing occurs x

28. Homework ; find the rule for converting static logic block into H/L and L/H stages

33. Final stage carry calculation
Toggle stage
AND gate as PP+SP

34. All AND gates ready for fire with 0-> 1 from LSB
0-> >1 1 1 1 1 1
All AND gates ready for fire
with 0-> 1 from LSB 1

36. SP+SN
SP+PN+SN
HT register is half-transparent,
i.e., transparent to high input

38. Speed up techniques employed
1) Non-classical f/f SP
PP+SP ;
p-type precharge latch
2) Both OR and AND gate
implemented as //el TR’s
PN+SN ;
n-type precharge latch

40. 1. When all inputs are 0’s, or 1’s ; all flags := 1
2. When some are 0’s ; only those flags become 0’s
3. Max word output follows input when all input are the same,
While follows 1 when partial 1’s occur.
4. Min selector ; invert all inputs, select the max, invert it.

41. Compare & swap cell

42. 8-input pipelined sorter