Download presentation
Presentation is loading. Please wait.
1
Using FPGAs with Processors in YOUR Designs
Class 5: Your Designs 9/27/2013 Warren Miller
2
This Week’s Agenda 9/23/13 An Intro to FPGAs with Processors 9/24/13 Architecture Details 9/25/13 Tool Support 9/26/13 Application Examples 9/27/13 A Review of YOUR Designs
3
Today’s Topics Goals and Objectives
Understand the “best fit” for YOUR suggested applications Architecture Review Applications Positioning Review Your Designs
4
Altera Arria V Architecture
Dual ARM Cortex-A9 CPU Cores 512 KB shared L2 cache with ECC 64 KB scratch RAM with ECC Multiport SDRAM controller DMA controller (+ most HPPs) Flash controller NAND Flash controller SD/SDIO/MMC controller 2x 10/100/1000 Ethernet MAC 2x USB OTG 4x I2C controller 2x UART 2x SPI masters, 2x SPI slaves 7x general-purpose timers 4x watchdog timers Up to 134 general-purpose I/O (GPIO) HPS Interfaces to FPGA HB AMBA AXI (32, 64, 128bit) LL AMBA AXI (32bit) FPGA to HPS SDRAM Controller
5
Altera Arria V Applications
Video Surveillance IP Camera with WDR and HD video Advanced analytics Wireless Infrastructure Remote Radio LTE Mobile backhaul Wireline Communications Router, Edge Equipment, Access Broadcast Studio, Video Conference Professional Audio/Video Defense and Aerospace Night Vision, Secure Communications Intelligence, Instrumentation Medical Diagnostic Imaging, Instrumentation Compute and Storage Multifunction printer Chassis Management Dual Processor Main and support processor Many processor support peripherals Common L2 Cache Autonomous High Performance Peripherals Programmable Communications Channel Augmented Functions within FPGA Bridging and Protocol Processing 1G Enet MAC, USB OTG, Hard PCIe, SerDes External Memory Support SDRAM, Flash, NAND Flash, SD/SDIO/MMC Interfaces to FPGA AMBA Bus, SDRAM Controller, etc. Variable Precision DSP Blocks 9x9, 18x18, 27x27, 36x36, 64-bt Accumulator Low Power SerDes Less than 105mW per channel at 6Gbps Less than 165mW per channel at 10Gbps Less than 170mW per channel at 12.5Gbps
6
SmartFusion2 Architecture
Encryption, Error Detection And Low Power Control Hardened MCU SEU Protected SRAM Blocks FPGA Logic SEU-Free Flash FPGA Configuration Memory SECDED Memory Interface SerDes Channels
7
Microsemi SmartFusion2 Applications
Military Security and Reliability Industrial Communications Aviation Space Reliability Processor, HPMS, FPGA Fabric Control and Bridging, Enhanced Processing Special Features Design and Data Security Root-of-Trust Secure key storage Physically Unclonable Function (PUF) Differential Power Analysis (DPA) Protection Reliability SEU immune zero FIT Flash Configuration SEU Protected memories Hard DDR2/3 Controllers with SECDED
8
Xilinx Zynq Architecture
Dual-core ARM Cortex-A9 with Cache On-Chip memory Boot ROM, 256 KB RAM External Memory Interface Flash, DRAM IO Peripherals UART, SPI, I2C, USB, Enet DMA AMBA Interconnect Programmable Logic PCI Express Block Serial Transceivers Up to 16 receivers and transmitters Supports up to 12.5 Gb/s data Analog to Digital Converters On-chip voltage and temp sensing Up to 17 external differential inputs Up to 1 Msps conversion rate
9
Xilinx Zynq Applications
Automotive Advanced Driver Assistance Consumer Equipment Factory Automation Broadcast Professional Cameras Enterprise Video Conferencing Monitors and Projectors Digital Signage 4K2K Ultra-HDTV Military Radios Medical Imaging Wired Communications Wireless Communications AVB Routers, Switches, Encoders Dual Processor Main and support processor Many processor support peripherals Autonomous High Performance Peripherals Dual AMBA Interconnect Busses Analog Peripherals Augmented Functions within FPGA Bridging and Protocol Processing 2x 1G Enet MAC, Hard PCIe Gen2, SerDes Flash Controller SDRAM Controller Interfaces to FPGA AXI Ports (GP, HP) Security Features AES, SHA, RSA
10
Your Applications Thanks for your input!
Many good applications- too many to cover individually Tried to combine some applications so I can cover as many key elements as possible Hopefully will provide you with a good starting point… Get an eval board and start using the tools!
11
Your Design #1 Multi-processing Design
Example: 16 separate processes to compress results from high-speed ADCs (but could be any high-speed serial data stream) Could do it in the CPUs (if they are fast enough) Better to use the FPGA fabric and construct several processing engines (use block memory for buffering) The CPUs can focus on scheduling and ‘over watch’ Can use external DRAM is buffering requirements are demanding
12
Your Design #1 JESD204x SerDes Memory Processing Bus CPU JESD204x
DMA Xilinx Zynq Target FPGA Fabric for stream processing DMA for block data movement One CPU for peripheral management Configuration of processing blocks One CPU for algorithm control Data stream bandwidth? Algorithm requirements? Power requirements? Prototyping? CPU DDR Controller Peripherals DDR Memory USB, SPI, Ethernet
13
Xilinx Zynq Family
14
Xilinx Zynq Family
15
Xilinx Zynq Family
16
Xilinx Zynq Family
17
Your Design #2 Space Application Between 10 – 50MHz
Error Detection and Correction for external SRAM Signal acquisition Balance performance and Power consumption Program in C or assembly
18
Your Design #2 Bus CPU JESD204x SerDes Memory with ECC DMA
Processing (HDLC) SmartFusion2 Target Radiation protected NVM configuration Serial port for Data Acquisition Built-in ECC functions One CPU for algorithm control (50MHz) Redundancy required? Power requirements? Flash*Freeze Prototyping? Peripherals DDR Controller with ECC UART, CAN, Ethernet, I2C DDR Memory
19
Your Design #3 Medical Application Portable equipment Bio Sensing
Low Power and efficient performance Security Wireless Graphics User Interface (LCD, Keypad)
20
Your Design #3 SmartFusion2 Target Low Power and Secure NVM
Flash*Freeze Low Power Secure Bit Stream One CPU for algorithm control (150MHz) DSP Functions? Wireless Protocol? Reliability and Safety?
21
Your Design #4 Audio Processing (Test Equipment) Spectral Acquisition
Spectral Analysis Data Storage and Communication GUI Balance performance and Power consumption Program in C or assembly
22
Your Design #4 Multi-Channel Audio ADC Initial Processing Bus CPU DSP
DMA Altera Arria Target Audio DSP Open CL for DSP development Shared DDR Controller One CPU for User Interface Once CPU for DSP over watch Audio processing required? Power requirements? Prototyping? CPU Peripherals DDR Controller Industrial Ethernet, Control Panel DDR Memory
23
Your Design #5 Environmental Sensor
Vibration, Humidity, Temperature, Magnetic Log sensor readings Set trip points for wireless alarm Central control collects data and dumps logs Low Power, Low Performance Program in C or assembly
24
Your Design #5 ADC Sensors Peripherals Bus CPU I2C/SPI Sensors DMA
MCU Target AtoD Conversion for Sensors I2C or SPI for Sensors On-chip Data Flash Low-Power Sleep mode Efficient data processing Low Pin count, Low Cost Simple Power Requirement Battery operation Timers Peripherals RTC Wireless
25
Additional Resources Altera Arria Web Page Altera Arria Development Kits Microsemi SmartFusion2 Web Page Microsemi SmartFusion2 Development Kits Xilinx Zynq Web Page Xilinx Zynq Development Kits All Programmable Planet Warren’s CEC Course on Application Specific Programmable Logic Devices
26
DONE! This Week’s Agenda
9/23/13 An Intro to FPGAs with Processors 9/24/13 Architecture Details 9/25/13 Tool Support 9/26/13 Application Examples 9/27/13 A Review of YOUR Designs DONE!
Similar presentations
