1. Ch1. Fundamentals of Computer Design 3. Principles (5)
ECE562/468 Advanced Computer Architecture
Prof. Honggang Wang
Ch1. Fundamentals of Computer Design 3. Principles (5)
ECE Department
University of Massachusetts Dartmouth 285 Old Westport Rd. North Dartmouth, MA
Slides based on the PowerPoint Presentations created by David Patterson as part of the Instructor Resources for the textbook by Hennessy & Patterson
Updated by Honggang Wang.
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2. Administrative Issues (02/04/2016)
Xing - Fall09
Administrative Issues (02/04/2016)
Project team set-up due Thursday, Feb. 11
Each group has 3-4 group members
Two types of groups: ECE 468 and ECE 562
If you registered ECE 468, you only can join ECE 468 group
If you registered ECE 562, you only can join ECE 562 group
Your group leader must send me an about your group information by 02/11
If you missed the first week class, go to the course website for syllabus and 1st lecture.
My office hours:
T./TH. 11 am-12:45 pm, Fri. 1:00-1:30 pm
Background Review Lecture

3. Review of Lecture #2 In the #2 lecture, we covered the
Xing - Fall09
Review of Lecture #2
In the #2 lecture, we covered the
Careful, quantitative comparisons: Performance
Compute Mean
Benchmark

4. Comp. Arch. is an Integrated Approach
What really matters is the functioning of the complete system
hardware, runtime system, compiler, operating system, and application
Computer architecture is not just about transistors, individual instructions, or particular implementations
E.g., Original RISC projects replaced complex instructions with a compiler + simple instructions
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5. Computer Architecture is Design & Analysis
Architecture is an iterative process:
Searching the space of possible designs
At all levels of computer systems
Creativity
Cost /
Performance
Analysis
Good Ideas
Mediocre Ideas
Bad Ideas
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6. Measurement & Evaluation
Our ECE 562/468 Focus
Understanding the design techniques, machine structures, technology factors, evaluation methods that will determine the form of computers in 21st Century
Parallelism
Technology
Programming
Languages
Applications
Interface Design
(ISA)
Computer Architecture:
• Organization
• Hardware/Software Boundary
Compilers
Operating
Measurement & Evaluation
History
Systems
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7. 1) Taking Advantage of Parallelism
Increasing throughput of server computer via multiple processors or multiple disks
Detailed HW design
Carry lookahead adders uses parallelism to speed up computing sums from linear to logarithmic in number of bits per operand
Multiple memory banks searched in parallel in set-associative caches
Pipelining: overlap instruction execution to reduce the total time to complete an instruction sequence.
Not every instruction depends on immediate predecessor  executing instructions completely/partially in parallel possible
Classic 5-stage pipeline: 1) Instruction Fetch (Ifetch), 2) Register Read (Reg), 3) Execute (ALU), 4) Data Memory Access (Dmem), 5) Register Write (Reg)
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8. Pipelined Instruction Execution
Time (clock cycles)
Reg
ALU
DMem
Ifetch
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 6
Cycle 7
Cycle 5
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9. Limits to pipelining
Hazards prevent next instruction from executing during its designated clock cycle
Structural hazards: attempt to use the same hardware to do two different things at once
Data hazards: Instruction depends on result of prior instruction still in the pipeline
Control hazards: Caused by delay between the fetching of instructions and decisions about changes in control flow (branches and jumps).
Time (clock cycles) I n s t r. O r d e
Reg
ALU
DMem
Ifetch
Reg
ALU
DMem
Ifetch
Reg
ALU
DMem
Ifetch
Reg
ALU
DMem
Ifetch
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10. 2) The Principle of Locality
Program access a relatively small portion of the address space at any instant of time.
Two Different Types of Locality:
Temporal Locality (Locality in Time): If an item is referenced, it will tend to be referenced again soon (e.g., loops, reuse)
Spatial Locality (Locality in Space): If an item is referenced, items whose addresses are close by tend to be referenced soon (e.g., array access)
Last 30 years, HW relied on locality for memory performance. P
MEM $
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11. Levels of the Memory Hierarchy
Capacity
Access Time
Cost
Staging
Transfer Unit
CPU Registers
100s Bytes
300 – 500 ps ( ns)
Upper Level
Registers
prog./compiler
1-8 bytes
Instr. Operands
faster
L1 Cache
L1 and L2 Cache
10s-100s K Bytes
~1 ns - ~10 ns
$1000s/ GByte
cache cntl
32-64 bytes
Blocks
L2 Cache
cache cntl
bytes
Blocks
Main Memory
G Bytes
80ns- 200ns
~ $100/ GByte
Memory OS
4K-8K bytes
Pages
Disk
10s T Bytes, 10 ms (10,000,000 ns)
~ $1 / GByte
Disk
user/operator
Mbytes
Files
Larger
Tape
infinite
sec-min
~$1 / GByte
Tape
Lower Level
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12. 3) Focus on the Common Case
Common sense guides computer design
Since its engineering, common sense is valuable
In making a design trade-off, favor the frequent case over the infrequent case
E.g., Instruction fetch and decode unit used more frequently than multiplier, so optimize it 1st
E.g., If database server has 50 disks / processor, storage dependability dominates system dependability, so optimize it 1st
Frequent case is often simpler and can be done faster than the infrequent case
E.g., overflow is rare when adding 2 numbers, so improve performance by optimizing more common case of no overflow
May slow down overflow, but overall performance improved by optimizing for the normal case
What is frequent case and how much performance improved by making case faster => Amdahl’s Law
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13. 4) Amdahl’s Law
Amdahl’s law sates that the performance improvement to be gained from using some faster mode of execution is limited by the fraction of the items the faster mode can be used.
Best you could ever hope to do: the law of diminishing returns
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14. Amdahl’s Law example New CPU 10X faster
I/O bound server, so 60% time waiting for I/O
Apparently, its human nature to be attracted by 10X faster, vs. keeping in perspective its just 1.6X faster
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15. 5) Processor performance equation The Iron Law
CPI
5) Processor performance equation The Iron Law
inst count
Cycle time
CPU time = Seconds = Instructions x Cycles x Seconds
Program Program Instruction Cycle
Inst Count CPI Clock Rate Program X Compiler X (X) Inst. Set. X X Organization X X Technology X
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16. Two Examples: Amdahl’s Law [p.40] Iron Law [43]
Measurements
FP: %, 4 CPI
where FPSQR: 2%, 20 CPI
others: CPI
Two Alternatives
FPSQR: decrease to 2 CPI
FP: decrease to 2.5 CPI
Winner: FP
Same speedup
Two Alternatives
FPSQR: 20%, 10X
FP: %, 1.6X
Winner: FP
Q1: What is the difference ?
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17. Summary Computer Architecture >> instruction sets
Computer Architecture skill sets are different
5 Quantitative principles of design
Quantitative approach to design
Technology tracking and anticipation
Computing at the crossroads from sequential to parallel computing
Salvation requires innovation in many fields, including computer architecture

18. Next Topics Things To Do Find your partners for the class project
Xing - Fall09
Next Topics
Ch2. Instruction-Level Parallelism & Its Exploitation
Things To Do
Find your partners for the class project
Feb. 11, Thursday ( me the team information)
Check out the class website about
lecture notes
reading assignments
Homework 1 assignment