1. TEL62 project update
Franco Spinella
Elena Pedreschi
INFN-Pisa

2. TEL62 Evolution of the LHCb TELL1 :
FPGAs: EP3SL110 F1152C4 (same for PP and SL)
DDR: 2Gb or 4Gb DDR2 SO-DIMM modules on socket
Power: newer DCDC (48->1.1, 48->1.8, 48->2.5) , linear regulators for PLLs and QPLL
Doubled connectivity PP<->SL
PPs connected in daisy chain
Aux connector for additional plugin (serializer …)
Many other small changes …
See note NA "From TELL1 to TEL62“ E.Pedreschi – M. Sozzi – F. Spinella
TDAQ

3. Synclink-FPGA BLOCK DIAGRAM = new DC PP-FPGA PPclock TDAQ 15-12-2010
DDR2
Synclink-FPGA
ECS
TTCRX
GBIT (EXT. SIZE)
AUX CONN.
PPclock
= new
TDAQ

4. STATUS Design: Schematics are complete (almost …)
SL swap is in progress, some details are still missing
Will be circulated at the end of the swaps
TDAQ

5. FPGA pin assignment PP: pins defined, assigned and swapped
SL: pins defined, assigned, still NOT swapped (98% used !!!) PP SL
TDAQ

6. PCB PCB design started few weeks ago PP section is complete:
PP-FPGA (swapped), DC, DDR2, local power supply
x4 already done
SL already placed, routing in progress
All lines are required to have 50 Ohm inpedance (100 Ohm if differential)
TDAQ

7. PCB
TDAQ

8. PCB DDR2 routing needs great accuracy
We are following Micron raccomendations and Altera stratix III reference design
TDAQ

9. Parts procurement
We plan to build prototypes ASAP and cards in 2011
Some parts already bought: fpgas (few), DCDC (many), CERN components (all), CPPC + GLUE (all)
Some parts are difficult to find: e.g. CCPC connectors -> we need to find a broker or something
TDAQ

10. CONCLUSIONS
The PCB design should be ready for production mid January (maybe a little optimistic)
If we manage to have all the parts by the end of January we could start the tests of the first prototype in February
Accurate tests need a lot of firmware…
TDAQ