Presentation is loading. Please wait.

Presentation is loading. Please wait.

Process technology Physical layout with L-Edit

Published byMeghan Gibbs Modified over 6 years ago

Similar presentations

Presentation on theme: "Process technology Physical layout with L-Edit"— Presentation transcript:

1 Process technology Physical layout with L-Edit
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Process technology Physical layout with L-Edit T. Delbruck Neuromorphic Engineering 2 Lecture 2 1

2 Analog Chip CAD design tools
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Analog Chip CAD design tools Design Verification S-Edit Schematic editor T-Spice Circuit simulator LVS Layout vs. Schematic L-Edit Layout editor DRC Design rule checker Extract Netlist extractor Mask layout 2

3 Neuromoprhic Engineering 2, Process Technology
9/10/2018 L-Edit 3

4 Neuromoprhic Engineering 2, Process Technology
9/10/2018 Bardeen and Brattain ~1950 1947 4

5 Neuromoprhic Engineering 2, Process Technology
9/10/2018 A finished wafer 2000 ~2000 5

6 Superficial historical timeline of fabrication technology development
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Superficial historical timeline of fabrication technology development 1930 1940 1950 1960 1970 1980 1990 2000 2010 Lilienfield patents on field-effect transistors Ohl Silicon PN junction Bell labs, Bardeen Brattain make point contact bipolar bipolar Phillbrick tube opamp Fairchild founded 30u Accutron watch Kilby/TI integrated circuit, Noyce/Fairchild planar process 63 Widlar/National uA701 opamp Intel founded ($34B sales 2004) 10u Faggin silicon gate DEC PDP-11 nMOS ‘73 Intel 8008 ‘74 National LM324 opamp ‘78 Intel 8086 CMOS 1u TSMC fab founded ($6B sales 2003) IBM’s CMP planarization enables many metal levels Motorola PowerPC 601 0.25u 90nm 50nm? 6

7 Neuromoprhic Engineering 2, Process Technology
9/10/2018 NTRS Roadmap 7

8 Cost of chip production
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Cost of chip production At 1000 wafers/month (lots of parts!) ~$600/6 inch 0.25u wafer=~$3.50/cm2 Add for packaging ~0.25 cents/pin for QFP (about most expensive) Add for testing $200/hour for 256 pin mixed signal tester; about 1 second to move sites (6 inch wafer ~ 180 cm2, 8 inch ~ 310 cm2) From numbers like these, you can compute production price of your chip Thanks to Chuck Neugebauer for prices ca. 2006 8

9 Moore’s “law” (more like observation)
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Moore’s “law” (more like observation) Number of transistors per chip doubles every 1.5 to 2 years Cost/bit drops 29%/year True for last 45 years! 0.25u 90-65nm 2000 Tobi’s extrapolation 9

10 Neuromoprhic Engineering 2, Process Technology
9/10/2018 Inverter layout P-Select (NOT N-select) N-Select (implant) Contact Poly N-well Via Metal1 Active (thin oxide) Metal2 10

11 Neuromoprhic Engineering 2, Process Technology
9/10/2018 S D G holes electrons n+ p+ p+ n+ n+ p+ n well p well p--- epi p+ wafer

12 CMOS process technology
Neuromoprhic Engineering 2, Process Technology 9/10/2018 CMOS process technology A wafer is photolithograpically processed using a set of masks A typical process has ~15-40 masks Each mask patterns a layer The exact process steps vary, but a single photolithographic step uses a common technology for patterning 13

13 Neuromoprhic Engineering 2, Process Technology
9/10/2018 What can a process do? Pattern Photolithography exposes photoresist to removes it selectively Deposit Use chemical vapor deposition (CVD) to coat wafer with layer of stuff Implant Shoots ions into silicon with controlled energy Diffuse Heats wafer to diffuse implants Etch Uses plasmas or wet etches to remove silicon or oxide Polish CMP (Chemical Mechanical Polishing) uses wet slurry and rotating wheels to smooth surface 14

14 Neuromoprhic Engineering 2, Process Technology
9/10/2018 Photolithography A photoresist is spun onto the wafer It is exposed using the mask with a stepper The photoresist is chemically developed Where the resist has been exposed, it is washed away (this is a positive resist) The remaining resist blocks an implant or etch 15

15 Fabrication step by step
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Fabrication step by step Wafer prep Active region isolation by LOCOS or STI N and P Wells Threshold adjustment Gate and poly LDD Source & Drain diffusions Contacts Metal interconnect Higher metal levels & Passivation 16

16 Neuromoprhic Engineering 2, Process Technology
9/10/2018 Gettering Gathers impurities like Au, Na away from surface by diffusion. Scratched back of wafer along with oxygen interstitials act as nucleation sites. Creates denuded zone at surface. 17

17 Fabrication step by step
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Fabrication step by step Wafer prep Active region isolation by LOCOS or STI N and P Wells Threshold adjustment Gate and poly LDD Source & Drain diffusions Contacts Metal interconnect Higher metal levels & Passivation 18

18 Neuromoprhic Engineering 2, Process Technology
9/10/2018 Contact N-Select Poly N-well Via Metal1 Active (aka Diff) Metal2 19

19 Silicon nitride blocks Si oxidation
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Silicon nitride blocks Si oxidation Si3N4 can be deposited and patterned by photolithography It can be very selectively etched without etching silicon After patterning, it efficiently blocks oxidation of silicon 20

20 LOCOS (Local Oxidation of Silicon)
Neuromoprhic Engineering 2, Process Technology 9/10/2018 LOCOS (Local Oxidation of Silicon) Used extensively in the past and still used for many processes 21

21 STI (Shallow Trench Isolation)
Neuromoprhic Engineering 2, Process Technology 9/10/2018 STI (Shallow Trench Isolation) Harder than LOCOS but now used for deep submicron processes 22

22 LOCOS Silicon Nitride Growth
Neuromoprhic Engineering 2, Process Technology 9/10/2018 LOCOS Silicon Nitride Growth PDG 23

23 LOCOS Silicon Nitride Etch
Neuromoprhic Engineering 2, Process Technology 9/10/2018 LOCOS Silicon Nitride Etch PDG 24

24 LOCOS FOX (Field Oxide) growth
Neuromoprhic Engineering 2, Process Technology 9/10/2018 LOCOS FOX (Field Oxide) growth FOX 25

25 Fabrication step by step
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Fabrication step by step Wafer prep Active region isolation by LOCOS or STI N and P Wells Threshold adjustment Gate and poly LDD Source & Drain diffusions Contacts Metal interconnect Higher metal levels & Passivation 26

26 Neuromoprhic Engineering 2, Process Technology
9/10/2018 Contact N-Select Poly Via N-well P-well=!N-well Metal1 Active Metal2 27

27 Neuromoprhic Engineering 2, Process Technology
9/10/2018 P-well implant PDG 28

28 Neuromoprhic Engineering 2, Process Technology
9/10/2018 N-well implant PDG 29

29 Well drive-in diffusion
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Well drive-in diffusion PDG 30

30 Active formation after LOCOS
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Active formation after LOCOS PDG 31

31 Fabrication step by step
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Fabrication step by step Wafer prep Active region isolation by LOCOS or STI N and P Wells Threshold adjustment Gate and poly LDD Source & Drain diffusions Contacts Metal interconnect Higher metal levels & Passivation 32

32 Neuromoprhic Engineering 2, Process Technology
9/10/2018 VthN adjust N-select PDG 33

33 Neuromoprhic Engineering 2, Process Technology
9/10/2018 VthP adjust !N-select (P-select) PDG 34

34 Fabrication step by step
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Fabrication step by step Wafer prep Active region isolation by LOCOS or STI N and P Wells Threshold adjustment Gate oxide and poly LDD Source & Drain diffusions Contacts Metal interconnect Higher metal levels & Passivation PDG 35

35 Neuromoprhic Engineering 2, Process Technology
9/10/2018 Poly Contact N-Select N-well Via Metal1 Active Metal2 36

36 Gate oxide strip and grow
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Gate oxide strip and grow PDG 37

37 Gate oxide is tricky… Nowadays is about 10 atomic layers thick
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Gate oxide is tricky… Nowadays is about 10 atomic layers thick Dangling bonds create havoc by allowing charge to stick Plummer, Deal, Griffen Bravman 38

38 Poly deposition and doping
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Poly deposition and doping PDG 39

39 Neuromoprhic Engineering 2, Process Technology
9/10/2018 Poly etch Poly PDG 40

40 Fabrication step by step
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Fabrication step by step Wafer prep Active region isolation by LOCOS or STI N and P Wells Threshold adjustment Gate and poly LDD Source & Drain diffusions Contacts Metal interconnect Higher metal levels & Passivation 41

41 LDD (Lightly Doped Drain)
Neuromoprhic Engineering 2, Process Technology 9/10/2018 LDD (Lightly Doped Drain) LDD is used in sub-micron processes to reduce the electric field at transistor drains It reduces damage caused by hot electrons It is necessary because power supply voltage has not dropped as quickly as process dimensions 42

42 Neuromoprhic Engineering 2, Process Technology
9/10/2018 N LDD implant 43

43 Neuromoprhic Engineering 2, Process Technology
9/10/2018 P LDD implant 44

44 Si02 prep for sidewall spacer formation
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Si02 prep for sidewall spacer formation PDG 45

45 Sidewall Si02 anisotropic etch
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Sidewall Si02 anisotropic etch PDG 46

46 Fabrication step by step
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Fabrication step by step Wafer prep Active region isolation by LOCOS or STI N and P Wells Threshold adjustment Gate and poly LDD Source & Drain diffusions Contacts Metal interconnect Higher metal levels & Passivation 47

47 Neuromoprhic Engineering 2, Process Technology
9/10/2018 N-Select P-Select=!N-Select Contact Poly N-well Via Metal1 Active Metal2 48

48 Screen oxide + N S/D implant
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Screen oxide + N S/D implant N-select PDG 49

49 Neuromoprhic Engineering 2, Process Technology
9/10/2018 P S/D implant !N-select PDG 50

50 Activation and diffusion of dopants
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Activation and diffusion of dopants PDG 51

51 Removal of screen oxide
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Removal of screen oxide PDG 52

52 Fabrication step by step
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Fabrication step by step Wafer prep Active region isolation by LOCOS or STI N and P Wells Threshold adjustment Gate and poly LDD Source & Drain diffusions Contacts Metal interconnect Higher metal levels & Passivation PDG 53

53 Neuromoprhic Engineering 2, Process Technology
9/10/2018 Contact N-Select Poly N-well Via Metal1 Active Metal2 54

54 Neuromoprhic Engineering 2, Process Technology
9/10/2018 Ti deposition PDG 55

55 Ti +N2 reaction to form TiN or TiSi2
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Ti +N2 reaction to form TiN or TiSi2 PDG 56

56 Neuromoprhic Engineering 2, Process Technology
9/10/2018 TiN etch These ‘local interconnects’ are also called Silicidation. They reduce resistance. Called Salicide for Active and Polycide for Poly. PDG 57

57 Conformal Si02 deposition
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Conformal Si02 deposition PDG 58

58 Neuromoprhic Engineering 2, Process Technology
9/10/2018 CMP polish PDG 59

59 Neuromoprhic Engineering 2, Process Technology
9/10/2018 CMP PDG 60

60 Fabrication step by step
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Fabrication step by step Wafer prep Active region isolation by LOCOS or STI N and P Wells Threshold adjustment Gate and poly LDD Source & Drain diffusions Contacts Metal interconnect Higher metal levels & Passivation PDG 61

61 Neuromoprhic Engineering 2, Process Technology
9/10/2018 Contact N-Select Poly N-well Via Metal1 Active Metal2 62

62 Contact patterning and etch
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Contact patterning and etch Contact PDG 63

63 TiN barrier metal + W (Tungsten) depositions
Neuromoprhic Engineering 2, Process Technology 9/10/2018 TiN barrier metal + W (Tungsten) depositions W=tungsten 64

64 CMP polish of contact metal
Neuromoprhic Engineering 2, Process Technology 9/10/2018 CMP polish of contact metal Ti/N/W prevents ‘wormholes’ where Al makes spikes into Si 65

65 Al deposit, pattern , and etch (Metal1)
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Al deposit, pattern , and etch (Metal1) Metal1 66

66 Fabrication step by step
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Fabrication step by step Wafer prep Active region isolation by LOCOS or STI N and P Wells Threshold adjustment Gate and poly LDD Source & Drain diffusions Contacts Metal interconnect Higher metal levels & Passivation 67

67 Neuromoprhic Engineering 2, Process Technology
9/10/2018 Contact N-Select Poly N-well Via Metal1 Active Metal2 68

68 Further metals plus passivation
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Further metals plus passivation 69

69 Credits for illustrations
Neuromoprhic Engineering 2, Process Technology 9/10/2018 Credits for illustrations Plummer, Deal, Griffin Silicon VLSI Technology A. Bergemont in Liu, Indiveri, Kramer, Delbruck, Douglas, Analog VLSI van Zant, Microchip Fabrication 70

Download ppt "Process technology Physical layout with L-Edit"

Similar presentations

CMOS Fabrication EMT 251.

CMOS Fabrication EMT 251.
ECE 6466 “IC Engineering” Dr. Wanda Wosik

ECE 6466 “IC Engineering” Dr. Wanda Wosik
Process Flow Steps Steps –Choose a substrate  Add epitaxial layers if needed –Form n and p regions –Deposit contacts and local interconnects –Deposit.

Process Flow Steps Steps –Choose a substrate  Add epitaxial layers if needed –Form n and p regions –Deposit contacts and local interconnects –Deposit.
Simplified Example of a LOCOS Fabrication Process

Simplified Example of a LOCOS Fabrication Process
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Digital Integrated Circuits A Design Perspective Manufacturing Process July 30, 2002.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Digital Integrated Circuits A Design Perspective Manufacturing Process July 30, 2002.
CMOS Process at a Glance

CMOS Process at a Glance
Chapter 2 Modern CMOS technology

Chapter 2 Modern CMOS technology
VLSI Design Lecture 2: Basic Fabrication Steps and Layout

VLSI Design Lecture 2: Basic Fabrication Steps and Layout
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 CMOS Process Manufacturing Process.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 CMOS Process Manufacturing Process.
Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.

Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.
Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,

Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,
1 Lecture 5: IC Fabrication The Transistor Revolution First transistor Bell Labs, 1948 © Rabaey: Digital Integrated Circuits 2nd.

1 Lecture 5: IC Fabrication The Transistor Revolution First transistor Bell Labs, 1948 © Rabaey: Digital Integrated Circuits 2nd.
CSE477 L05 IC Manufacturing.1Irwin&Vijay, PSU, 2002 CSE477 VLSI Digital Circuits Fall 2002 Lecture 05: IC Manufacturing Mary Jane Irwin ( www.cse.psu.edu/~mji.

CSE477 L05 IC Manufacturing.1Irwin&Vijay, PSU, 2002 CSE477 VLSI Digital Circuits Fall 2002 Lecture 05: IC Manufacturing Mary Jane Irwin (
Device Fabrication Example

Device Fabrication Example
EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.
ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems Micron-scale devices which transduce an environmental.

ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems Micron-scale devices which transduce an environmental.
ISAT 436 Micro-/Nanofabrication and Applications MOS Transistor Fabrication David J. Lawrence Spring 2001.

ISAT 436 Micro-/Nanofabrication and Applications MOS Transistor Fabrication David J. Lawrence Spring 2001.
Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.

Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.
CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.

CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #2. Chip Fabrication  Silicon Ingots  Wafers  Chip Fabrication Steps (FEOL, BEOL)  Processing Categories 

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #2. Chip Fabrication  Silicon Ingots  Wafers  Chip Fabrication Steps (FEOL, BEOL)  Processing Categories 

Similar presentations

Ads by Google