1. The Silicon-on-Sapphire Technology:
The ASIC development is based on the 0.25 μm Silicon-on-Sapphire (SOS) technology, the UltraCMOSTM GC process from Peregrine Semiconductors Corp.
This SOS technology has been evaluated to be radiation tolerant in our applications for the LAr and the Inner Detector upgrades with the sapphire substrate grounded.
It has a fT of 90 GHz which is much faster than that of the bulk silicon CMOS with the same feature size. It has advantage over bulk silicon technology in implementing LC based PLL circuits.
Requirements in ATLAS upgrades:
Liquid Argon:
128 detector 40 16bit  82 Gbps
Parallel data format and rate are unknown at this moment, but must be at ~500 MHz to match the output of 82 Gbps.
Redundancy in fiber channels to prevent single point failure.
A 12-way ribbon with single channel at ~8 Gbps will be needed. A 10G Fiber has been identified (SMU + Oxford collaboration). The expertise to deal with ribbon exists in the present Tracker readout.
FEB power budget: 80W. The Link should not take a large fraction of it.
Radiation Tolerance TID = 4 Mrad, NIEL = neutron/cm2
Inner Tracker:
Above 3 Gbps for each stave.
Prefer the optical link to be at the end of the stave, or even farther out, for concerns about radiation damage to VCSELs.
Small package form factor to fit in tight space. The Versatile Link mechanical design takes this into consideration already.
Channel redundancy is needed to achieve high reliability. VTx from Versatile Link, in SFP+ package, offers two channels naturally.
Input signal will be ~300 MHz over ~ 1m.
Power: should be low enough that it works without external cooling.
Radiation Tolerance ~50 Mrad and neutron/cm2.
NMOS
PMOS
Comparison of various device characteristics.
Symbol “⌾” means the best, “×” indicates the least good.
Transistor high frequency characteristics of an SOS device and a bulk Si device.
OKI technical Review, Oct.2004/Issue 200 Vol.71 No.4, posted at
SOS LOC
An ASIC being developed for ultra-fast, low power and radiation tolerant optical data link systems for the LHC upgrade, based on the Silicon-on-Sapphire 0.25 μm commercial CMOS technology.
Jingbo Ye
The ASIC development is funded through the US-ATLAS R&D program in the LAr for the LHC upgrade.
The technology evaluation is funded through the DOE ADR program to evaluate the SOS technology for ASIC development for HEP.
Other institutions have expressed interest in the SOS technology, funding has been requested.
The second prototype of the LOC, the LOC2, is planned to be submitted June 09 through a MPW. The design is done by 1 FTE (Datao Gong), with a recent addition of 0.6 FTE (Andy Liu).
There is a strong interest of University of Milan and INFN in exploiting all the potential SOS technology has to offer for this application and also for the development of radiation tolerant SRAM memory.
The collaboration has started and few circuit solutions are being designed and will be submitted together with the LOC in June.
The Link-on-Chip (LOC) ASIC being developed at SMU to meet the requirements in the upgrades:
The LOC design and development status:
Full schematics level simulations and post-layout studies on key components have been performed.
The output waveform (differential CML)
with the 2.5 GHz clock (complementary CMOS) to show the width of one bit.
The system with a LOC
Single LOC, 5 Gbps, less than 80 mW/Gbps for the Tracker
16:1
The VCO post-layout phase noise
The VCO layout
The VCO post-layout output waveform
PLL
The VCO post-layout frequency vs Vctrl
Supper LOC, or SLOC, offers Gbps, less than 50 mW/Gbps, for the LAr
The divide-by-2 layout with complementary CMOS clock
The post-layout simulation indicates that this divider works at 3 GHz (period = 330 ps) in the S-S corner. The requirement is 2.5 GHz.
LC based PLL may deliver data at 8 Gbps in a single fiber channel. This is currently under investigation at SMU.